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From: Bjorn Helgaas <bhelgaas@google.com>
To: Wolfgang Denk <wd@denx.de>, Shaohua Li <shli@kernel.org>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: Re: VIA chipset with Root Port under a bridge
Date: Thu, 22 Aug 2013 15:49:24 -0600	[thread overview]
Message-ID: <CAErSpo49W9iYWUfVRCALr9Nkvuzs38MwzNUAXLgr91BRiRFtFQ@mail.gmail.com> (raw)
In-Reply-To: <CAErSpo53GpzdinvmQNX=DfJSsTUOzKng6LT1jrDSM8aU1ZUJiA@mail.gmail.com>

[replace Shaohua's dead Intel address with @kernel.org address; please
reply to this, not the original]

On Thu, Aug 22, 2013 at 3:47 PM, Bjorn Helgaas <bhelgaas@google.com> wrote:
> Shaohua, your commit 8e822df700 references a VIA chipset with a Root
> Port under a bridge, and that commit adds a special case to disable
> ASPM for that situation.
>
> I know this is pretty old (the commit is from 2009), but do you have
> any more details about that system?  A pointer to the original problem
> report, lspci output, dmesg output, etc.?
>
> I'm concerned because other parts of PCI make assumptions about Root
> Port topology, e.g., in MPS configuration, and we might need to make
> similar changes elsewhere.
>
> Bjorn

  reply	other threads:[~2013-08-22 21:49 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-08-22 21:47 VIA chipset with Root Port under a bridge Bjorn Helgaas
2013-08-22 21:49 ` Bjorn Helgaas [this message]
2013-08-23  1:06   ` Shaohua Li
2013-08-23 21:18     ` Wolfgang Denk
  -- strict thread matches above, loose matches on Subject: below --
2013-09-06 13:07 Wolfgang Denk
2013-09-06 15:17 ` Bjorn Helgaas

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