From: Tim Harvey <tharvey@gateworks.com>
To: linux-pci@vger.kernel.org
Subject: legacy PCI device behind a bridge not getting a valid IRQ on imx host controller
Date: Wed, 28 Aug 2024 14:40:33 -0700 [thread overview]
Message-ID: <CAJ+vNU2YVpQ=csr-O65L_pcNFWbFMvHK4XO44cbfUfPKwuw6vg@mail.gmail.com> (raw)
Greetings,
I have a user that is using an IMX8MM SoC (dwc controller) with a
miniPCIe card that has a PEX8112 PCI-to-PCIe bridge to a legacy PCI
device and the device is not getting a valid interrupt.
The PCI bus looks like this:
00.00.0: 16c3:abcd (rev 01)
01:00.0: 10b5:8112
^^^ PEX8112 x1 Lane PCI bridge
02:00.0: 4ddc:1a00
02:01.0: 4ddc:1a00
^^^ PCI devices
lspci -vvv -s 02:00.0:
02:00.0 Communication controller: ILC Data Device Corp Device 1a00 (rev 10)
Subsystem: ILC Data Device Corp Device 1a00
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium
>TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 0
Region 0: Memory at 18100000 (32-bit, non-prefetchable)
[disabled] [size=256K]
Region 1: Memory at 18180000 (32-bit, non-prefetchable)
[disabled] [size=4K]
^^^ 'Interrupt: pin A routed to IRQ 0' is wrong
I found an old thread from 2019 on an NVidia forum [1] where the same
thing occurred and Nvidia's solution was a patch to the dwc driver to
call pci_fixup_irqs():
diff --git a/drivers/pci/dwc/pcie-designware-host.c
b/drivers/pci/dwc/pcie-designware-host.c
index ec2e4a61aa4e..a72ba177a5fd 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -477,6 +477,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
if (pp->ops->scan_bus)
pp->ops->scan_bus(pp);
+ pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
+
pci_bus_size_bridges(bus);
pci_bus_assign_resources(bus);
Since that time the pci/dwc drivers have changed quite a bit;
pci_fixup_irqs() was changed to pci_assign_irq() called now from
pcie_device_probe() and dw_pcie_host_init() calls commit init
functions.
While I don't have the particular card in hand described above yet to
test with, I did manage to reproduce this on an imx6dl soc (same dwc
controller and driver) connected to a TI XIO2001 with an Intel I210
behind it and see the exact same issue.
Does anyone understand why legacy PCI interrupt mapping behind a
bridge isn't working here?
Best regards,
Tim
[1] https://forums.developer.nvidia.com/t/xavier-not-routing-pci-interrupts-across-pex8112-bridge/78556
next reply other threads:[~2024-08-28 21:40 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-28 21:40 Tim Harvey [this message]
2024-08-29 21:22 ` legacy PCI device behind a bridge not getting a valid IRQ on imx host controller Bjorn Helgaas
2024-08-29 21:43 ` Frank Li
2024-08-29 22:00 ` Bjorn Helgaas
2024-08-29 22:21 ` Tim Harvey
2024-08-30 15:52 ` Frank Li
2024-08-30 16:11 ` Tim Harvey
2024-08-30 15:49 ` Frank Li
2024-08-30 16:06 ` Manivannan Sadhasivam
2024-08-30 16:15 ` Bjorn Helgaas
2024-08-30 1:50 ` Hongxing Zhu
2024-08-30 16:03 ` Tim Harvey
2024-08-30 16:14 ` Frank Li
2024-09-06 19:37 ` Tim Harvey
2024-09-06 19:58 ` Bjorn Helgaas
2024-09-10 16:50 ` Tim Harvey
2024-09-10 23:04 ` Bjorn Helgaas
2024-09-12 23:28 ` Tim Harvey
2024-09-23 17:56 ` Tim Harvey
2024-09-26 22:30 ` Bjorn Helgaas
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