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[209.85.221.178]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-52922dc587dsm2271396e0c.48.2025.04.23.02.38.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Apr 2025 02:38:54 -0700 (PDT) Received: by mail-vk1-f178.google.com with SMTP id 71dfb90a1353d-5240a432462so791171e0c.1; Wed, 23 Apr 2025 02:38:54 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCV2xUvrRnNfuG2YkFhU0KoMsCboPevG94+nRwIe50dwLku/DC9h16HmDpNlYRwo6KfgqyyWlbm56mWB++Hc@vger.kernel.org, AJvYcCXNwqjNkyRZMzHeJlzfDrpy2JLrL8kQgSJpLPXT+k1KnolYyBfPd71KkOJM950c/4+lEDPVmVOM9fuO@vger.kernel.org, AJvYcCXSo16ZKAQKzRiWAUL2QxiH239eeTqUXbZqNOMBisWzGDf0GdKzQ5vEZjKgyTwJtymoGl2yXTnLq/+xd0QN9jWQn4Q=@vger.kernel.org, AJvYcCXm7YevtdbycO+NfhXqUrCcMtvNXlPn7B0UsNfKJY1D99aVTNdMEhRqPQvBMVbWhWbTCeNx4pXCUcn5@vger.kernel.org X-Received: by 2002:a05:6122:2029:b0:50d:39aa:7881 with SMTP id 71dfb90a1353d-52a69ee4ed3mr1464819e0c.0.1745401133893; Wed, 23 Apr 2025 02:38:53 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250406144822.21784-1-marek.vasut+renesas@mailbox.org> <20250406144822.21784-2-marek.vasut+renesas@mailbox.org> <20250410204845.GA1027003-robh@kernel.org> <40c400ab-8770-4595-9a4c-004e6157c348@mailbox.org> In-Reply-To: <40c400ab-8770-4595-9a4c-004e6157c348@mailbox.org> From: Geert Uytterhoeven Date: Wed, 23 Apr 2025 11:38:42 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: ATxdqUEdpJzlYJJPC9uQQHl7BMlq_ah4RVyU1yK01V61iQt1LxPiUJbnjP-RWIo Message-ID: Subject: Re: [PATCH v2 1/4] dt-bindings: PCI: rcar-gen4-pci-host: Document optional aux clock To: Marek Vasut Cc: Rob Herring , Marek Vasut , linux-arm-kernel@lists.infradead.org, =?UTF-8?Q?Niklas_S=C3=B6derlund?= , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= , Aradhya Bhatia , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Heiko Stuebner , Junhao Xie , Kever Yang , Krzysztof Kozlowski , Kuninori Morimoto , Lorenzo Pieralisi , Magnus Damm , Manivannan Sadhasivam , Neil Armstrong , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Marek, On Sun, 13 Apr 2025 at 11:29, Marek Vasut wrote: > On 4/10/25 10:48 PM, Rob Herring wrote: > > On Sun, Apr 06, 2025 at 04:45:21PM +0200, Marek Vasut wrote: > >> Document 'aux' clock which are used to supply the PCIe bus. This > >> is useful in case of a hardware setup, where the PCIe controller > >> input clock and the PCIe bus clock are supplied from the same > >> clock synthesiser, but from different differential clock outputs: > >> > >> ____________ _____________ > >> | R-Car PCIe | | PCIe device | > >> | | | | > >> | PCIe RX<|=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D|>= PCIe TX | > >> | PCIe TX<|=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D|>= PCIe RX | > >> | | | | > >> | PCIe CLK<|=3D=3D=3D=3D=3D=3D.. ..=3D=3D=3D=3D=3D=3D|>PCIe CLK = | > >> '------------' || || '-------------' > >> || || > >> ____________ || || > >> | 9FGV0441 | || || > >> | | || || > >> | CLK DIF0<|=3D=3D=3D=3D=3D=3D'' || > >> | CLK DIF1<|=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D'' > >> | CLK DIF2<| > >> | CLK DIF3<| > >> '------------' > >> > >> The clock are named 'aux' because those are one of the clock listed in > >> Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml which > >> fit closest to the PCIe bus clock. According to that binding document, > >> the 'aux' clock describe clock which supply the PMC domain, which is > >> likely PCIe Mezzanine Card domain. > > > > Pretty sure that PMC is "power management controller" given it talks > > about low power states. > > > > > >> > >> Tested-by: Niklas S=C3=B6derlund > >> Signed-off-by: Marek Vasut > >> --- > >> NOTE: Shall we patch Documentation/devicetree/bindings/pci/snps,dw-pci= e-common.yaml > >> instead and add 'bus' clock outright ? > > > > Based on the diagram, this has nothing to do with the specific > > controller. It should also probably a root port property, not host > > bridge. > How would you suggest I describe the clock which supply the PCIe bus > clock lane (CLK DIF1 in the diagram) , which have to be enabled together > with clock which supply the PCIe controller input clock lane (CLK DIF0) ? I think Rob wants you to add clocks/clock-names for this to dtschema/schemas/pci/pci-bus-common.yaml. Then you can have pcie@M,N subnode(s) with num-lanes, clock, and clock-names describing the PCIe endpoint(s)? git grep "pcie*@[0-9],[0-9]" -- $(git grep -l num-lanes -- Documentation/ ) Does that make sense? Thanks! Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds