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[209.85.217.52]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-506290ef371sm314407137.5.2025.08.08.05.04.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Aug 2025 05:04:05 -0700 (PDT) Received: by mail-vs1-f52.google.com with SMTP id ada2fe7eead31-50307b67169so1707076137.1; Fri, 08 Aug 2025 05:04:05 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCUJOmr/bSpucsYDmPtIj5BMgnv1BYj40K4jIYCpArWRauF/fxDu6gRsx51gxHlWqXCedJkgEkNyv3/LUrI3@vger.kernel.org, AJvYcCUdsmSwV5UurRyJjuooCCl1mPDvRiahxqNffUusOlFZ1BhLlxTYWzclQupE4HSyddhbDnZu5f0olRFE@vger.kernel.org, AJvYcCV+T/I0BUNntHWtEhgeH5GheZ7wumr4uTN4LyD9XxWletLTQskMtGyL2K77WVY1wvyeMKSCEp0JxeaF@vger.kernel.org, AJvYcCWOJ5zaR+1BusaAuih1DL9xdLZfJpgszeIood06B6XwYG3Dns4TSFXoAowfA+8jzme9aUjbDfl8Y6DMV1Irn+4c0vg=@vger.kernel.org, AJvYcCX9We9JB1eznnnf+E+CVAHs3Ef9ih/2KwG4rlrFBmvZfnG6mkN7U5R9rUthvNOyrzrMwQHnj2bZRx8O@vger.kernel.org X-Received: by 2002:a05:6102:c89:b0:4fb:df6d:61e9 with SMTP id ada2fe7eead31-5060cc8f424mr967777137.1.1754654644981; Fri, 08 Aug 2025 05:04:04 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250709132449.GA2193594@bhelgaas> <2e0d815a-774a-4e31-92f1-71e0772294c7@kernel.org> <0addc570-a3c6-4d7e-9cbd-06eedd2447bb@tuxon.dev> In-Reply-To: <0addc570-a3c6-4d7e-9cbd-06eedd2447bb@tuxon.dev> From: Geert Uytterhoeven Date: Fri, 8 Aug 2025 14:03:53 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: Ac12FXxvhlSsjlxIyp9wLVrjxx1brBJSnSBO2bel6v02fDMzhy9BrWS7nxQ7HtU Message-ID: Subject: Re: [PATCH v3 4/9] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add documentation for the PCIe IP on Renesas RZ/G3S To: Claudiu Beznea Cc: Krzysztof Kozlowski , Bjorn Helgaas , bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, lizhi.hou@amd.com, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Claudiu Beznea , Wolfram Sang Content-Type: text/plain; charset="UTF-8" Hi Claudiu, On Fri, 8 Aug 2025 at 13:44, Claudiu Beznea wrote: > On 09.07.2025 16:43, Krzysztof Kozlowski wrote: > > On 09/07/2025 15:24, Bjorn Helgaas wrote: > >> On Wed, Jul 09, 2025 at 08:47:05AM +0200, Krzysztof Kozlowski wrote: > >>> On 08/07/2025 18:34, Bjorn Helgaas wrote: > >>>> On Fri, Jul 04, 2025 at 07:14:04PM +0300, Claudiu wrote: > >>>>> From: Claudiu Beznea > >>>>> > >>>>> The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express > >>>>> Base Specification 4.0. It is designed for root complex applications and > >>>>> features a single-lane (x1) implementation. Add documentation for it. > >>>> > >>>>> +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml > >>>> > >>>> The "r9a08g045s33" in the filename seems oddly specific. Does it > >>>> leave room for descendants of the current chip that will inevitably be > >>>> added in the future? Most bindings are named with a fairly generic > >>>> family name, e.g., "fsl,layerscape", "hisilicon,kirin", "intel, > >>>> keembay", "samsung,exynos", etc. > >>>> > >>> > >>> Bindings should be named by compatible, not in a generic way, so name is > >>> correct. It can always grow with new compatibles even if name matches > >>> old one, it's not a problem. > >> > >> Ok, thanks! > >> > >> I guess that means I'm casting shade on the "r9a08g045s33" compatible. > >> I suppose it means something to somebody. > > > > Well, I hope it matches the name of the SoC, from which the compatible > > should come :) > > The r9a08g45s33 is the part number of a device from the RZ/G3S group. This > particular device from RZ/G3S group supports PCIe. > > In the RZ/G3S group there are more SoC variants (each with its own part > number). Not all support PCIe. To differentiate b/w PCIe and non-PCIe > variants it has been chosen to use the full part number here. > > The available RZ/G3S part numbers are listed in Table 1.1 Product Lineup at [1] > > (The following steps should be followed to access the manual: > 1/ Click the "User Manual" button > 2/ Click "Confirm"; this will start downloading an archive > 3/ Open the downloaded archive > 4/ Navigate to r01uh1014ej*-rzg3s-users-manual-hardware -> Deliverables > 5/ Open the file r01uh1014ej*-rzg3s.pdf) > > We use a similar compatible scheme in other drivers. > > Geert, I may be wrong. Please correct me otherwise, as I don't have the > full picture of this. > > Maybe, the other variant would be to use "renesas,rzg3s-pcie", or maybe a > more generic one "renesas,rz-pcie" (though I think this last one is too > generic). Both would be too generic for the myriad of RZ devices. AFAIU, the R9A08G045Sxx variants are really the same SoC, with some hardware modules disabled/nonfunctional. This is typically handled by: 1. Using the base part number (r9a08g045) in the compatible value, 2. Having the device node in the base .dtsi, 3. Deleting nodes in the variant-specific .dtsi file when needed (see e.g. arch/arm64/boot/dts/renesas/r9a09g047{,e[35]7}.dtsi) Hence as R9A08G045S13, R9A08G045S17, R9A08G045S33, and R9A08G045S37 all have PCIe, I think it is more appropriate to use "renesas,r9a08g045-pcie" as the compatible value than "renesas,r9a08g045s33-pcie". > Geert, please let us know if you have some suggestions here with regards to > the compatible. The IP on RZ/G3S is compatible also with the one in RZ/V2H, > RZ/G3E. RZ/V2H and RZ/G3E can use "renesas,r9a09g057-pcie" resp. "renesas,r9a09g047-pcie", with "renesas,r9a08g045-pcie" as a fallback. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds