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[209.85.217.48]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-557bd8e11a3sm537444e0c.10.2025.10.23.01.00.33 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Oct 2025 01:00:33 -0700 (PDT) Received: by mail-vs1-f48.google.com with SMTP id ada2fe7eead31-5a3511312d6so231463137.3 for ; Thu, 23 Oct 2025 01:00:33 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCVIewO6maY2GQJSzk1ztm1GulTZspgk1/v9dD9rbW/OybqtDE9OwxdTYNcKq8ncXpPcwZp3SUl5Kgo=@vger.kernel.org X-Received: by 2002:a05:6102:32d3:b0:5d5:f40a:4cf1 with SMTP id ada2fe7eead31-5d7dd6a4e59mr6656672137.24.1761206432910; Thu, 23 Oct 2025 01:00:32 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20251007133657.390523-1-claudiu.beznea.uj@bp.renesas.com> <20251007133657.390523-3-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20251007133657.390523-3-claudiu.beznea.uj@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 23 Oct 2025 10:00:21 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: AS18NWB9_OOBrClG3W5gj81JVaeCg1e2FLiq_rBpovw0Id2oH40EKE5zSy4p5SM Message-ID: Subject: Re: [PATCH v5 2/6] PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver To: Claudiu Cc: lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Wolfram Sang Content-Type: text/plain; charset="UTF-8" Hi Claudiu, On Tue, 7 Oct 2025 at 15:37, Claudiu wrote: > From: Claudiu Beznea > > The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express > Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions > only as a root complex, with a single-lane (x1) configuration. The > controller includes Type 1 configuration registers, as well as IP > specific registers (called AXI registers) required for various adjustments. > > Hardware manual can be downloaded from the address in the "Link" section. > The following steps should be followed to access the manual: > 1/ Click the "User Manual" button > 2/ Click "Confirm"; this will start downloading an archive > 3/ Open the downloaded archive > 4/ Navigate to r01uh1014ej*-rzg3s-users-manual-hardware -> Deliverables > 5/ Open the file r01uh1014ej*-rzg3s.pdf > > Link: https://www.renesas.com/en/products/rz-g3s?queryID=695cc067c2d89e3f271d43656ede4d12 > Tested-by: Wolfram Sang > Signed-off-by: Claudiu Beznea Thanks for your patch! > --- /dev/null > +++ b/drivers/pci/controller/pcie-rzg3s-host.c > +static void rzg3s_pcie_irq_compose_msi_msg(struct irq_data *data, > + struct msi_msg *msg) > +{ > + struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(data); > + struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); > + u32 drop_mask = RZG3S_PCI_MSIRCVWADRL_ENA | > + RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA; This should include bit 2 (which is hardwired to zero (for now)), so I think you better add #define RZG3S_PCI_MSIRCVWADRL_ADDR GENMASK(31, 3) > + u32 lo, hi; > + > + /* > + * Enable and msg data enable bits are part of the address lo. Drop > + * them. > + */ > + lo = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRL) & ~drop_mask; ... and use FIELD_GET() with the new definition here. > + hi = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRU); > + > + msg->address_lo = lo; > + msg->address_hi = hi; > + msg->data = data->hwirq; > +} Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds