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AJvYcCVi9u2+LDMiZZ3uNiSh5LYL1YUem8vXsDXIz6l6VW33bmd5/II1lsauLxFQdLihDdrM5yzoMbaVB4s=@vger.kernel.org X-Gm-Message-State: AOJu0Yy6+9LVgWnBq85ptl6krj68kZzJ5ywvIVMpvwOsi0jKJjoAWYiJ vQZEqrhZiizwWlJOjgzciy0PfM/h00Zjb+T7UTDQiLkUmQqK9e1TJXCbdCWpdRbt5l/jKEJt5IU cR+YYIyyfMke8TF0pbAE2wd120OFhwXU= X-Gm-Gg: ASbGnctCMh3HvagH/EtOPkEJnjXLg8gSVonJXT5VuiLmMe9i+w3MnrjAgtF3EeG8ADa p0RZGp9qgmCgbGVkEjsjgf8scemXpWncx7L1Ss10Nl2SfJ7Sop8wxDs6W1rS+pIS6K5AxB/6AGo 8YS+IOgIw9PLYF/4bq7gqsSu7cnEpWDjqQaNI5Ji14LNF+K9G3wLd+3/D8NfvLf6P26mGNbvmkW WQmKuodtYFlJYWXbu8c0Y/A6aVMUfZdheNxpYEH1ir40pUYn9FpCTsrT72g2ehcK9hA7Q== X-Google-Smtp-Source: AGHT+IEYzJae7VoT/c7FHoFZ2w1f+vGPYbQGnE984l0qzu5gM1i4HI97k5jQZaiikEMv2TwzZxE5MWhZESWWNIE+YQ8= X-Received: by 2002:a17:907:1c1e:b0:b2b:59b5:ae38 with SMTP id a640c23a62f3a-b6d51bfb0e1mr629125966b.40.1761286636888; Thu, 23 Oct 2025 23:17:16 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250926072905.126737-1-linux.amoon@gmail.com> <20250926072905.126737-4-linux.amoon@gmail.com> <6eqqafz2dojo533fw2j7say3p37simug5bol2s5dvcpac77jzb@2x22ekyl4qdq> In-Reply-To: <6eqqafz2dojo533fw2j7say3p37simug5bol2s5dvcpac77jzb@2x22ekyl4qdq> From: Anand Moon Date: Fri, 24 Oct 2025 11:47:02 +0530 X-Gm-Features: AS18NWB79LzUXZfNM_Vk4QnYlquHYcZbCYFtcNRut2QcVzty8nJpzlwr2rljOfc Message-ID: Subject: Re: [PATCH v1 3/5] PCI: tegra: Use readl_poll_timeout() for link status polling To: Manivannan Sadhasivam Cc: Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , "open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "open list:TEGRA ARCHITECTURE SUPPORT" , open list , Mikko Perttunen Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Manivannan, On Tue, 21 Oct 2025 at 07:13, Manivannan Sadhasivam wrote= : > > On Mon, Oct 20, 2025 at 05:47:15PM +0530, Anand Moon wrote: > > Hi Manivannan, > > > > Thanks for your review comment. > > > > On Sun, 19 Oct 2025 at 13:20, Manivannan Sadhasivam w= rote: > > > > > > On Fri, Sep 26, 2025 at 12:57:44PM +0530, Anand Moon wrote: > > > > Replace the manual `do-while` polling loops with the readl_poll_tim= eout() > > > > helper when checking the link DL_UP and DL_LINK_ACTIVE status bits > > > > during link bring-up. This simplifies the code by removing the open= -coded > > > > timeout logic in favor of the standard, more robust iopoll framewor= k. > > > > The change improves readability and reduces code duplication. > > > > > > > > Cc: Thierry Reding > > > > Cc: Mikko Perttunen > > > > Signed-off-by: Anand Moon > > > > --- > > > > v1: dropped the include header file. > > > > --- > > > > drivers/pci/controller/pci-tegra.c | 37 +++++++++++---------------= ---- > > > > 1 file changed, 14 insertions(+), 23 deletions(-) > > > > > > > > diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/contr= oller/pci-tegra.c > > > > index 07a61d902eae..b0056818a203 100644 > > > > --- a/drivers/pci/controller/pci-tegra.c > > > > +++ b/drivers/pci/controller/pci-tegra.c > > > > @@ -2169,37 +2169,28 @@ static bool tegra_pcie_port_check_link(stru= ct tegra_pcie_port *port) > > > > value |=3D RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; > > > > writel(value, port->base + RP_PRIV_MISC); > > > > > > > > - do { > > > > - unsigned int timeout =3D TEGRA_PCIE_LINKUP_TIMEOUT; > > > > + while (retries--) { > > > > + int err; > > > > > > > > - do { > > > > - value =3D readl(port->base + RP_VEND_XP); > > > > - > > > > - if (value & RP_VEND_XP_DL_UP) > > > > - break; > > > > - > > > > - usleep_range(1000, 2000); > > > > - } while (--timeout); > > > > - > > > > - if (!timeout) { > > > > + err =3D readl_poll_timeout(port->base + RP_VEND_XP, v= alue, > > > > + value & RP_VEND_XP_DL_UP, > > > > + 1000, > > > > > > The delay between the iterations had range of (1000, 2000), now it wi= ll become > > > (250, 1000). How can you ensure that this delay is sufficient? > > > > > I asked if the timeout should be increased for the loops, but Mikko > > Perttunen said that 200ms delay is fine. > > > > readl_poll_timeout() internally uses usleep_range(), which transforms the= 1000us > delay into, usleep_range(251, 1000). So the delay *could* theoretically b= e 251us > * 200 =3D ~50ms. > > So I doubt it will be sifficient, as from the old code, it looks like the > hardware could take around 200ms to complete link up. > Instead of implementing a busy-waiting while loop with udelay, a more efficient and responsive approach is to use the readl_poll_timeout() function. This function periodically polls a memory-mapped address, waiting for a condition to be met or for a specified timeout to occur. If there are any issues with HW, we could extend the timeout to compensate. > - Mani Thanks -Anand > > -- > =E0=AE=AE=E0=AE=A3=E0=AE=BF=E0=AE=B5=E0=AE=A3=E0=AF=8D=E0=AE=A3=E0=AE=A9= =E0=AF=8D =E0=AE=9A=E0=AE=A4=E0=AE=BE=E0=AE=9A=E0=AE=BF=E0=AE=B5=E0=AE=AE= =E0=AF=8D