From: Dan Williams <dan.j.williams@intel.com>
To: Amey Narkhede <ameynarkhede03@gmail.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
Vikram Sethi <vsethi@nvidia.com>,
Chris Browy <cbrowy@avery-design.com>,
linux-cxl@vger.kernel.org, Ben Widawsky <ben.widawsky@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Alex Williamson <alex.williamson@redhat.com>,
Shanker Donthineni <sdonthineni@nvidia.com>,
Linux PCI <linux-pci@vger.kernel.org>
Subject: Re: CXL Hot and Warm Reset Testing
Date: Sat, 14 Aug 2021 12:47:09 -0700 [thread overview]
Message-ID: <CAPcyv4iDZQuDvE9kBjpjTTWA4z7-aZ=AAon-OREObyzDWALfMw@mail.gmail.com> (raw)
In-Reply-To: <20210814111620.wn6422g3dbed52ex@archlinux>
On Sat, Aug 14, 2021 at 4:16 AM Amey Narkhede <ameynarkhede03@gmail.com> wrote:
>
> On 21/08/13 12:14PM, Bjorn Helgaas wrote:
> > [+cc Amey (working on PCI resets), linux-pci]
> >
> > On Fri, Aug 13, 2021 at 05:01:32PM +0000, Vikram Sethi wrote:
> > > Hi Dan,
> > >
> > > > -----Original Message-----
> > > > From: Dan Williams <dan.j.williams@intel.com>
> > > >
> > > > On Wed, Aug 11, 2021 at 9:42 AM Chris Browy <cbrowy@avery-design.com>
> > > > wrote:
> > > >
> > > > /sys/bus/pci/devices/$device/reset is a method to trigger PCI
> > > > device reset, but I do not expect that will ever gain CXL specific
> > > > knowledge.
> > > >
> > > CXL reset may need some thought, specially for devices that don't
> > > expose FLR but do expose CXL reset (while former does not affect
> > > CXL.cache/mem, the latter wipes out CXL.cache/mem state in the
> > > device and there is discoverability as to whether or not memory
> > > contents can be cleared as part of CXL reset). We may need a way of
> > > triggering CXL reset from userspace, and if the existing
> > > /sys/bus/pci/devices/$device/reset won't have knowledge of CXL
> > > reset, there still should be a prioritized order in the kernel in
> > > which CXL reset is attempted before more drastic resets like SBR.
> > > IIRC CXL reset can also impact all functions that use CXL.cache/mem,
> > > but not legacy PCIe functions on the device which do not use
> > > CXL.cache/mem (there is discoverability as to which functions are
> > > not impacted by CXL reset).
> > >
> > > Thanks,
> > > Vikram
>
> We can add new reset method and expose it to userspace via new 'reset_method'
> sysfs attribute introduced in this series
> https://lore.kernel.org/linux-pci/20210805162917.3989-1-ameynarkhede03@gmail.com/
It's not clear to me that's a suitable place for CXL reset though. CXL
reset wants to coordinate with the device's participation in a
potential interleave-set across multiple devices. So something like
/sys/bus/cxl/devices/memX/reset might be a better location for
coordinated CXL reset if needed. Again though, the primary use case
for userspace triggered reset is device assignment, and there are
better mechanisms to assign CXL.mem resources to a guest.
prev parent reply other threads:[~2021-08-14 19:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <DM5PR12MB2534D383B0226498DD7F2005BDFA9@DM5PR12MB2534.namprd12.prod.outlook.com>
2021-08-13 17:14 ` CXL Hot and Warm Reset Testing Bjorn Helgaas
2021-08-13 21:27 ` Dan Williams
2021-08-17 3:03 ` Vikram Sethi
2021-08-14 11:16 ` Amey Narkhede
2021-08-14 19:47 ` Dan Williams [this message]
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