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AJvYcCWGEUtULb5YCZT6t0IDemVAA3h1qTw5q72sZOZbpHwg2UdCRqlpeyeCd1PtfCb3U93jdrTQrRDf1lUvk4AFOfjPvDoGqtdxghj6 X-Gm-Message-State: AOJu0YwIaT3Wrb8J91c5JJMoYmFrg9xfEveClDWiCrUQ4luWYbJZ6Dgr crL5WYRPpWidHuQ1i4dUVpm8Ggh0p/y0iug+0cNBozcp0ZUdemH86v6P9DX6v9jhpYWU8zMw8dK 2bLqY7uqeR7han92+hK6qSkgEvAkj6d08tn3q2A== X-Google-Smtp-Source: AGHT+IFvTpixASaAP4xWWgQqjnNaP7m3tey7jFG8JbB1XlcOznYi4oLBuRU+2Lnv87Umzp1CJIcF/1QlHwBKcKC6VuI= X-Received: by 2002:a05:6902:2b0d:b0:e0b:4aa4:1704 with SMTP id 3f1490d57ef6-e0bde2909f8mr21646461276.18.1723004622627; Tue, 06 Aug 2024 21:23:42 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240719075200.10717-2-jhp@endlessos.org> <20240719080255.10998-2-jhp@endlessos.org> <20240805112456.00007cad@linux.intel.com> In-Reply-To: <20240805112456.00007cad@linux.intel.com> From: Jian-Hong Pan Date: Wed, 7 Aug 2024 12:23:06 +0800 Message-ID: Subject: Re: [PATCH v8 4/4] PCI/ASPM: Fix L1.2 parameters when enable link state To: Nirmal Patel Cc: Bjorn Helgaas , Johan Hovold , David Box , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= , Kuppuswamy Sathyanarayanan , Mika Westerberg , Damien Le Moal , Jonathan Derrick , Paul M Stillwell Jr , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux@endlessos.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Nirmal Patel =E6=96=BC 2024=E5=B9=B48=E6=9C= =886=E6=97=A5 =E9=80=B1=E4=BA=8C =E4=B8=8A=E5=8D=882:25=E5=AF=AB=E9=81=93= =EF=BC=9A > > On Fri, 2 Aug 2024 16:24:18 +0800 > Jian-Hong Pan wrote: > > > Jian-Hong Pan =E6=96=BC 2024=E5=B9=B47=E6=9C=8819= =E6=97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=884:04=E5=AF=AB=E9=81=93=EF=BC= =9A > > > > > > Currently, when enable link's L1.2 features with > > > __pci_enable_link_state(), it configs the link directly without > > > ensuring related L1.2 parameters, such as T_POWER_ON, > > > Common_Mode_Restore_Time, and LTR_L1.2_THRESHOLD have been > > > programmed. > > > > > > This leads the link's L1.2 between PCIe Root Port and child device > > > gets wrong configs when a caller tries to enabled it. > > > > > > Here is a failed example on ASUS B1400CEAE with enabled VMD: > > > > > > 10000:e0:06.0 PCI bridge: Intel Corporation 11th Gen Core Processor > > > PCIe Controller (rev 01) (prog-if 00 [Normal decode]) ... > > > Capabilities: [200 v1] L1 PM Substates > > > L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ > > > L1_PM_Substates+ PortCommonModeRestoreTime=3D45us > > > PortTPowerOnTime=3D50us L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- > > > ASPM_L1.2+ ASPM_L1.1- T_CommonMode=3D45us LTR1.2_Threshold=3D101376ns > > > L1SubCtl2: T_PwrOn=3D50us > > > > > > 10000:e1:00.0 Non-Volatile memory controller: Sandisk Corp WD Blue > > > SN550 NVMe SSD (rev 01) (prog-if 02 [NVM Express]) ... > > > Capabilities: [900 v1] L1 PM Substates > > > L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- > > > L1_PM_Substates+ PortCommonModeRestoreTime=3D32us > > > PortTPowerOnTime=3D10us L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- > > > ASPM_L1.2+ ASPM_L1.1- T_CommonMode=3D0us LTR1.2_Threshold=3D0ns > > > L1SubCtl2: T_PwrOn=3D10us > > > > > > According to "PCIe r6.0, sec 5.5.4", before enabling ASPM L1.2 on > > > the PCIe Root Port and the child NVMe, they should be programmed > > > with the same LTR1.2_Threshold value. However, they have different > > > values in this case. > > > > > > Invoke aspm_calc_l12_info() to program the L1.2 parameters properly > > > before enable L1.2 bits of L1 PM Substates Control Register in > > > __pci_enable_link_state(). > > > > > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D218394 > > > Signed-off-by: Jian-Hong Pan > > > --- > > > v2: > > > - Prepare the PCIe LTR parameters before enable L1 Substates > > > > > > v3: > > > - Only enable supported features for the L1 Substates part > > > > > > v4: > > > - Focus on fixing L1.2 parameters, instead of re-initializing whole > > > L1SS > > > > > > v5: > > > - Fix typo and commit message > > > - Split introducing aspm_get_l1ss_cap() to "PCI/ASPM: Introduce > > > aspm_get_l1ss_cap()" > > > > > > v6: > > > - Skipped > > > > > > v7: > > > - Pick back and rebase on the new version kernel > > > - Drop the link state flag check. And, always config link state's > > > timing parameters > > > > > > v8: > > > - Because pcie_aspm_get_link() might return the link as NULL, move > > > getting the link's parent and child devices after check the link > > > is not NULL. This avoids NULL memory access. > > > > > > drivers/pci/pcie/aspm.c | 15 +++++++++++++++ > > > 1 file changed, 15 insertions(+) > > > > > > diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c > > > index 5db1044c9895..55ff1d26fcea 100644 > > > --- a/drivers/pci/pcie/aspm.c > > > +++ b/drivers/pci/pcie/aspm.c > > > @@ -1411,9 +1411,15 @@ EXPORT_SYMBOL(pci_disable_link_state); > > > static int __pci_enable_link_state(struct pci_dev *pdev, int > > > state, bool locked) { > > > struct pcie_link_state *link =3D pcie_aspm_get_link(pdev); > > > + u32 parent_l1ss_cap, child_l1ss_cap; > > > + struct pci_dev *parent, *child; > > > > > > if (!link) > > > return -EINVAL; > > > + > > > + parent =3D link->pdev; > > > + child =3D link->downstream; > > > + > > > /* > > > * A driver requested that ASPM be enabled on this device, > > > but > > > * if we don't have permission to manage ASPM (e.g., on ACPI > > > @@ -1428,6 +1434,15 @@ static int __pci_enable_link_state(struct > > > pci_dev *pdev, int state, bool locked) if (!locked) > > > down_read(&pci_bus_sem); > > > mutex_lock(&aspm_lock); > > > + /* > > > + * Ensure L1.2 parameters: Common_Mode_Restore_Times, > > > T_POWER_ON and > > > + * LTR_L1.2_THRESHOLD are programmed properly before enable > > > bits for > > > + * L1.2, per PCIe r6.0, sec 5.5.4. > > > + */ > > > + parent_l1ss_cap =3D aspm_get_l1ss_cap(parent); > > > + child_l1ss_cap =3D aspm_get_l1ss_cap(child); > > > + aspm_calc_l12_info(link, parent_l1ss_cap, child_l1ss_cap); > > > + > > > link->aspm_default =3D pci_calc_aspm_enable_mask(state); > > > pcie_config_aspm_link(link, policy_to_aspm_state(link)); > > > > > > -- > > > 2.45.2 > > > > > > > Hi Nirmal and Paul, > > > > It will be great to have your review here. > > > > I had tried to "set the threshold value in vmd_pm_enable_quirk()" > > directly as Paul said [1]. However, it still needs to get the PCIe > > link from the PCIe device to set the threshold value. > > And, pci_enable_link_state_locked() gets the link. Then, it will be > > great to calculate and programm L1 sub-states' parameters properly > > before configuring the link's ASPM there. > > > > [1]: > > https://lore.kernel.org/linux-kernel/20240624081108.10143-2-jhp@endless= os.org/T/#mc467498213fe1a6116985c04d714dae378976124 > > > > Jian-Hong Pan > > Hi Jian-Hong Pan, > > I am not an LTR, ASPM expert, but this part looks good to me. > > Can you explain why you decided to move pci_enable_link_state_locked() > call down to out_state_change in vmd.c? The idea is setting all LTR related parameters before enabling the ASPM fea= ture. > Will it cause any issue if pci_find_ext_capability returns 0? If pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR) in vmd_pm_enable_quirk() returns 0, then the device is not a PCIe device. Then, it goes to: ... pci_enable_link_state_locked() __pci_enable_link_state() __pci_enable_link_state() uses pcie_aspm_get_link() to get the link between the PCIe bridge and the PCIe device. And, pcie_aspm_get_link() returns the link as a barrier. If pcie_aspm_get_link() does not get the link, then the device is a PCIe bridge, or not a PCIe device. Because the link is NULL, __pci_enable_link_state() returns with -EINVAL directly and will not configure/enable ASPM things. Jian-Hong Pan