From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BA0DDDD2; Thu, 13 Nov 2025 08:22:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763022145; cv=none; b=Sa6JzjEll7zaXHEgfWb0r7Yx8a1LQB9PMerSS28zddI9Bne0W8FZTZKZQ3vEXSVIlPqzY7AQnexMrgLebHqYKjWmCtPt/xWFULvBr4bzcosrVB8P2vLfSdToAwKf1GbVPEjhTcHL+DvFhRMVtIZzn6EXAtalaICuRGDQaC+yYJ0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763022145; c=relaxed/simple; bh=d4JnKSMp7EczeZ+X8w53xBnHhnFbumU9Pggc4oQpKbQ=; h=Mime-Version:Content-Type:Date:Message-Id:Subject:Cc:To:From: References:In-Reply-To; b=lLS+4WElFknCprJBxH+Pf7/m/Tc0HZAJAdcZfcZ2s4DoYcWwON95cujBcUqjIRNnht489oL7IHb9yeOWtz2MKZT0hzBlLK/o8Da/ZDbv9xK63+PNBCjVDw0RJODTW40cAtvAaSka10IZSBlIPFDFDEoGYOD4OvSSWnPQnawtSE8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CYi4tvZ6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CYi4tvZ6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 093DFC113D0; Thu, 13 Nov 2025 08:22:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763022145; bh=d4JnKSMp7EczeZ+X8w53xBnHhnFbumU9Pggc4oQpKbQ=; h=Date:Subject:Cc:To:From:References:In-Reply-To:From; b=CYi4tvZ6cDKihLTFtN9yc/+fc7S12dIzUx/ZvLrI+KPQhrz/UA2oftv68VgVrQN0n Mkjra2BqD5aRS6JEZu8lrHvc6Qzv0KP4rbDa2Ti0F3Giy6mHT4+nTRHM5O09ZNPJoz eaNtVd1m4YP7QcGKX18LbdyZsHqqDNFP61qMzZD7XC4nrgFDiiNYUGOGJv/YX8W+08 hYfRLkLZuIhdzfP2/sAfFm9FPttXOmyhJe1BCTg08iFe++LEcoj7LFyEQZDP2KGe97 f4XC9RpNyj/DRyoCLfHKG43DvoqfDHuEO6e2D/X7N2vMZ0HUesTaFgFR7ZUCsOjjU/ IJ5PVrRHqVPNA== Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 13 Nov 2025 19:22:15 +1100 Message-Id: Subject: Re: [PATCH] samples: rust: fix endianness issue in rust_driver_pci Cc: "Dirk Behme" , , , , , To: "Miguel Ojeda" , "Marko Turk" From: "Danilo Krummrich" References: <20251101214629.10718-1-mt@markoturk.info> In-Reply-To: On Wed Nov 12, 2025 at 8:56 PM AEDT, Miguel Ojeda wrote: > I guess we could potentially consider something like returning a > wrapper to force us to explicitly pick either LE or BE to prevent > things like this. In general, the I/O backend (e.g. MMIO, I2C, etc.) is supposed to take care of endianness. In the case of MMIO we (currently) always assume that the device is little-endian; this is also what the C functions used to implement the MMIO backend (e.g. readl()) assume, i.e. they always convert from little-endian = to CPU endianness. I don't think we should do anything else; the cases where we need to deal w= ith big-endian devices for MMIO should be extremely rare -- rare enough that th= ere aren't even corresponding *_be() implementations for all architectures. Given that, I think the proper fix is to drop the existing u32::from_le() c= all (that ended up in the sample driver by accident) and properly document the little-endian assumption of the MMIO backend. (Currently, this simply is the Io structure, but there is a patch series [1= ] from Zhi splitting things up, so we can start supporting arbitrary I/O backends.) @Marko: Two separate patches for this would be very welcome. :) [1] https://lore.kernel.org/all/20251110204119.18351-1-zhiw@nvidia.com/