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Fri, 31 Jul 2026 08:27:28 -0700 (PDT) Received: from localhost ([2a02:908:1578:7a40:eb03:fa54:642b:57ec]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1fd46836dcsm186119166b.63.2026.07.31.08.27.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 31 Jul 2026 08:27:27 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 31 Jul 2026 17:27:27 +0200 Message-Id: Subject: Re: [PATCH v2] PCI: imx6: Enable ASPM L1 only iff CLKREQ# is supported From: "Michal Gorlas" To: , "Michal Gorlas" Cc: , , X-Mailer: aerc 0.21.0 References: <20260731-l1-conditional-imx-v2-1-6016ee9148b2@9elements.com> <20260731135449.7A3B51F00A3A@smtp.kernel.org> In-Reply-To: <20260731135449.7A3B51F00A3A@smtp.kernel.org> On Fri Jul 31, 2026 at 3:54 PM CEST, sashiko-bot wrote: > Thank you for your contribution! Sashiko AI review found 1 potential issu= e(s) to consider: > - [Medium] ASPM L1 is conditionally disabled at boot but unconditionally = disabled upon resume, causing state inconsistency across power cycles. > -- > > --- Patch [1]: [PATCH v2] PCI: imx6: Enable ASPM L1 only iff CLKREQ# is s= upported --- > commit 7a899eb7e9f8116a0334832c7490e52f71ae751c > Author: Michal Gorlas > > PCI: imx6: Enable ASPM L1 only iff CLKREQ# is supported > > This commit conditionally disables ASPM L1 capabilities in the LNKCAP > register if supports-clkreq is not set in the device tree. It also disabl= es > L1 during resume for platforms advertising IMX_PCIE_FLAG_BROKEN_SUSPEND. > > Link: https://patch.msgid.link/20260719-l1-conditional-imx-v1-1-a55a57915= c68@9elements.com > >> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/control= ler/dwc/pci-imx6.c >> index 98e1db751132a..1fdcbcd2422e5 100644 >> --- a/drivers/pci/controller/dwc/pci-imx6.c >> +++ b/drivers/pci/controller/dwc/pci-imx6.c > [ ... ] >> @@ -1442,6 +1458,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *p= p) >> =20 >> imx_setup_phy_mpll(imx_pcie); >> =20 >> + if (!imx_pcie->supports_clkreq) >> + imx_pcie_disable_l1(pci); >> + >> return 0; >> =20 >> err_phy_off: > [ ... ] >> @@ -1748,6 +1767,7 @@ static int imx_pcie_resume_noirq(struct device *de= v) >> return ret; >> imx_pcie_deassert_core_reset(imx_pcie); >> imx_pcie_assert_perst(imx_pcie, false); >> + imx_pcie_disable_l1(imx_pcie->pci); > > [Severity: Medium] > Will this cause an inconsistent ASPM L1 state across power cycles? > > During boot in imx_pcie_host_init(), imx_pcie_disable_l1() is only called= if > imx_pcie->supports_clkreq is false. However, during resume here in > imx_pcie_resume_noirq(), the L1 capability is disabled unconditionally fo= r > platforms with IMX_PCIE_FLAG_BROKEN_SUSPEND. > > If a platform has supports_clkreq set to true, it would retain the L1 > capability at boot, but lose it unconditionally after a suspend/resume cy= cle. Platforms that set IMX_PCIE_FLAG_BROKEN_SUSPEND (i.MX6Q) do not set supports-clkreq in their DTs. So no, such scenario won't occur.