Re: [PATCH] PCI: pcie-altera: Set MPS to MPSS on Agilex 7 Root Ports

Mahesh Vaidya
2025-11-11T15:21:45Z

On 11-11-2025 01:36, Niklas Cassel wrote:
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> Hello Mahesh,
>
> On Mon, Nov 10, 2025 at 09:00:45AM -0800, Mahesh Vaidya wrote:
>> The Altera Agilex 7 Root Port (RP) defaults its Device Control
>> (DEVCTL) register's MPS setting to 128 bytes upon power-on.
>> When the kernel's PCIe core enumerates the bus (using the default
>> PCIE_BUS_DEFAULT policy), it observes this 128-byte current setting
>> and limits all downstream Endpoints to 128 bytes.
>> This occurs even if both the RP and the Endpoint support a higher MPSS
>> (e.g., 256 or 512 bytes), resulting in sub-optimal DMA performance.
>>
>> This patch fixes the issue by reading the RP's actual MPSS from its
>> Device Capability (DEVCAP) register and writing this value into the
>> DEVCTL register, overriding the 128-byte default value.
>> As this fix is called in driver's probe function before the PCI bus
>> is scanned, it ensures that when the kernel's PCI core enumerates the
>> downstream port, it reads the correct, maximum-supported MPS from the
>> RP's DEVCTL and can negotiate the optimal MPS for the Endpoint.
> Could you please review and test this series from Hans:
> https://lore.kernel.org/linux-pci/20251104165125.174168-1-18255117159@163.com/
>
> It tries to address the exact same problem that you are describing here.
Thanks, Niklas, for bringing this patch series to my attention.
I tested it on my hardware, and it resolves the issue for me.

Tested-by: Mahesh Vaidya <mahesh.vaidya@altera.com>
>
>
> Kind regards,
> Niklas