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charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: OlvEL+vOg0sQav9a6HHDouLZxASlm/T+ZnDtR74n5TNAeyyHQG5fv8SNDnaiK2vU52uzzgR4dNwYDd3r7HA9n2/Fhzs8f7/JsozGEGC2KNX/zl19f+tON3evGttgvofCqPwUVpn/OVPdjq8iY0JJXJjGL77co6N8BSBL7WUZUYB9Cp0O/9MqetV3M06kVFLUzrOeU+badHsWask1Jr0xz4A9549lTKHhTAoci3hVL2RDZxlfnZoWzkOy0txsjsURBtBhcXUwFvUMCeuV6LkNk2fiNxjIUGlVQb6lKGX9EUiH05idxokK7eJMYn/2MsIcHXsw8bfWpYjl1tlHkuwj6LHqR2g1ExD0ptlO8tNEowR8YINGt7xEop20ncyUjmAThapW5Ga9uNVuVK2PEBs6l88+n4FaaK05FzQATwJT8lAy2FFp81mxoCpmYlnOOn2k+k9RlVXtO3AJWzPXrXn9yMUGUFqB6neepq+jezAGw3ZHXs3pKA1bf/3xvDGUDIds/9C9fzLoKUxxJf3nxdkN5QF1a12TL/TEPoye+AG8gm8Odm9t/Xyn79HSqH89yDDf70yutHXNxO57Wp2EMODxn/viQ08arquKremn9feu1w5c1MKP+43yzSC4YB/1i8Vv X-OriginatorOrg: fujitsu.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: OSAPR01MB7182.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 73e3cb82-8e9f-403a-2f20-08dc85302855 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Jun 2024 07:21:46.1239 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a19f121d-81e1-4858-a9d8-736e267fd4c7 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: sQ3Il8kRx07xEMR8i8cITzmuvLRKxKe6VXa9Sind5yJ/eeMdXKCfZ4cuQSs0vv+Dy/E0k/WgjkY+uClmIiXfFp0XQQyxOxPadTRg2CZt9RA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: OS3PR01MB8044 Jonathan Cameron wrote: > On Fri, 10 May 2024 16:37:10 +0900 > "Kobayashi,Daisuke" wrote: >=20 > > Add sysfs attribute for CXL 1.1 device link status to the cxl pci devic= e. > > > > In CXL1.1, the link status of the device is included in the RCRB mapped= to > > the memory mapped register area. Critically, that arrangement makes the > > link status and control registers invisible to existing PCI user toolin= g. > > > > Export those registers via sysfs with the expectation that PCI user > > tooling will alternatively look for these sysfs files when attempting t= o > > access to these CXL 1.1 endpoints registers. >=20 > The lspci support raced with this series and has landed. >=20 > https://github.com/pciutils/pciutils/commit/49efa87fcce4f7d5b351238668ae > 1d4491802b88 >=20 > A few follow up comments on suggestion to cache the offset, not the regis= ter > value > (which might change over time) > > > > Reviewed-by: Jonathan Cameron > > Signed-off-by: "Kobayashi,Daisuke" > > --- > > drivers/cxl/pci.c | 101 > ++++++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 101 insertions(+) > > > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > > index 2ff361e756d6..c10797adde2c 100644 > > --- a/drivers/cxl/pci.c > > +++ b/drivers/cxl/pci.c > > @@ -786,6 +786,106 @@ static int cxl_event_config(struct pci_host_bridg= e > *host_bridge, > > return 0; > > } > > > > +static ssize_t rcd_link_cap_show(struct device *dev, > > + struct device_attribute *attr, char *buf) > > +{ > > + struct cxl_dev_state *cxlds =3D dev_get_drvdata(dev); > > + struct cxl_memdev *cxlmd =3D cxlds->cxlmd; > > + struct device *endpoint_parent; > > + struct cxl_dport *dport; > > + struct cxl_port *port; > > + > > + port =3D cxl_mem_find_port(cxlmd, &dport); > > + if (!port) > > + return -EINVAL; > > + > > + endpoint_parent =3D port->uport_dev; > > + if (!endpoint_parent) > > + return -ENXIO; > > + > > + guard(device)(endpoint_parent); > > + if (!endpoint_parent->driver) > > + return -ENXIO; > > + > > + return sysfs_emit(buf, "%x\n", dport->rcrb.rcd_lnkcap); >=20 > If you follow the suggestion of caching the offset, not the register > content then, these are all very similar. Define one common > function which takes a u8 offset and call that from each of the > functions. >=20 > If you stick to separate caches (and ensure they are up to date), > then you can add a utility function to take the dev here and > get you to the rcrb structure. Then you can call that and only > have the final line in each instances of this code. >=20 Thank you for your comment. To confirm my understanding of the proposed implementation approach,=20 I would like to share my interpretation: - The values stored in `cxl_rcrb_info` should be the offsets of the registe= rs,=20 rather than the register values themselves. - Similar to aer, the values should be read from the memory-mapped region=20 using the offset when they are needed. - To achieve this, the offsets (like `cxl_rcrb_pcie_caps`) will be stored i= n `cxl_rcrb_info`=20 during initialization, and the memory-mapped region will be accessed within= the `rcd_*_show()` functions where the values are actually used. - Accessing the memory-mapped region only requires the `struct device *dev`= ,=20 so a common utility function will be created and used for this purpose. If the cost of accessing the memory-mapped region at runtime is not high, e= specially considering=20 the avoidance of the walk to find the offset, then I believe it is more rea= sonable to access=20 the memory-mapped region at runtime. Could you let me know if there are any errors in my understanding. If there are no issues, I will update the implementation with this approach= =20 and submit a v8 patch (hopefully tomorrow). > > +} > > +static DEVICE_ATTR_RO(rcd_link_cap); > > + > > +static ssize_t rcd_link_ctrl_show(struct device *dev, > > + struct device_attribute *attr, char *buf) > > +{ > > + struct cxl_dev_state *cxlds =3D dev_get_drvdata(dev); > > + struct cxl_memdev *cxlmd =3D cxlds->cxlmd; > > + struct device *endpoint_parent; > > + struct cxl_dport *dport; > > + struct cxl_port *port; > > + > > + port =3D cxl_mem_find_port(cxlmd, &dport); > > + if (!port) > > + return -EINVAL; > > + > > + endpoint_parent =3D port->uport_dev; > > + if (!endpoint_parent) > > + return -ENXIO; > > + > > + guard(device)(endpoint_parent); > > + if (!endpoint_parent->driver) > > + return -ENXIO; > > + > > + return sysfs_emit(buf, "%x\n", dport->rcrb.rcd_lnkctrl); > > +} > > +static DEVICE_ATTR_RO(rcd_link_ctrl); > > + > > +static ssize_t rcd_link_status_show(struct device *dev, > > + struct device_attribute *attr, char *buf) > > +{ > > + struct cxl_dev_state *cxlds =3D dev_get_drvdata(dev); > > + struct cxl_memdev *cxlmd =3D cxlds->cxlmd; > > + struct device *endpoint_parent; > > + struct cxl_dport *dport; > > + struct cxl_port *port; > > + > > + port =3D cxl_mem_find_port(cxlmd, &dport); > > + if (!port) > > + return -EINVAL; > > + > > + endpoint_parent =3D port->uport_dev; > > + if (!endpoint_parent) > > + return -ENXIO; > > + > > + guard(device)(endpoint_parent); > > + if (!endpoint_parent->driver) > > + return -ENXIO; > > + > > + return sysfs_emit(buf, "%x\n", dport->rcrb.rcd_lnkstatus); > > +} > > +static DEVICE_ATTR_RO(rcd_link_status); > > + > > +static struct attribute *cxl_rcd_attrs[] =3D { > > + &dev_attr_rcd_link_cap.attr, > > + &dev_attr_rcd_link_ctrl.attr, > > + &dev_attr_rcd_link_status.attr, > > + NULL > > +}; > > + > > +static umode_t cxl_rcd_visible(struct kobject *kobj, > > + struct attribute *a, int n) > > +{ > > + struct device *dev =3D kobj_to_dev(kobj); > > + struct pci_dev *pdev =3D to_pci_dev(dev); > > + > > + if (is_cxl_restricted(pdev)) > > + return a->mode; > > + > > + return 0; > > +} > > + > > +static struct attribute_group cxl_rcd_group =3D { > > + .attrs =3D cxl_rcd_attrs, > > + .is_visible =3D cxl_rcd_visible, > > +}; > > +__ATTRIBUTE_GROUPS(cxl_rcd); > > + > > static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device= _id > *id) > > { > > struct pci_host_bridge *host_bridge =3D > pci_find_host_bridge(pdev->bus); > > @@ -969,6 +1069,7 @@ static struct pci_driver cxl_pci_driver =3D { > > .id_table =3D cxl_mem_pci_tbl, > > .probe =3D cxl_pci_probe, > > .err_handler =3D &cxl_error_handlers, > > + .dev_groups =3D cxl_rcd_groups, > > .driver =3D { > > .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, > > },