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Wed, 27 Mar 2024 08:24:01 +0000 From: "Daisuke Kobayashi (Fujitsu)" To: 'Dan Williams' , "linux-cxl@vger.kernel.org" CC: "Yasunori Gotou (Fujitsu)" , "linux-pci@vger.kernel.org" , "mj@ucw.cz" Subject: RE: [PATCH v3 0/3] Display cxl1.1 device link status Thread-Topic: [PATCH v3 0/3] Display cxl1.1 device link status Thread-Index: AQHadFO/DLT7o3hEPUOdByLFlXQIcrFKez4AgACh9ZA= Date: Wed, 27 Mar 2024 08:24:01 +0000 Message-ID: References: <20240312080559.14904-1-kobayashi.da-06@fujitsu.com> <66031eca92f5a_4a98a29427@dwillia2-mobl3.amr.corp.intel.com.notmuch> In-Reply-To: <66031eca92f5a_4a98a29427@dwillia2-mobl3.amr.corp.intel.com.notmuch> Accept-Language: ja-JP, en-US Content-Language: ja-JP X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_1e92ef73-0ad1-40c5-ad55-46de3396802f_ActionId=ea787c2d-abe0-409f-93db-88f210c48f83;MSIP_Label_1e92ef73-0ad1-40c5-ad55-46de3396802f_ContentBits=0;MSIP_Label_1e92ef73-0ad1-40c5-ad55-46de3396802f_Enabled=true;MSIP_Label_1e92ef73-0ad1-40c5-ad55-46de3396802f_Method=Privileged;MSIP_Label_1e92ef73-0ad1-40c5-ad55-46de3396802f_Name=FUJITSU-PUBLIC?;MSIP_Label_1e92ef73-0ad1-40c5-ad55-46de3396802f_SetDate=2024-03-27T04:55:13Z;MSIP_Label_1e92ef73-0ad1-40c5-ad55-46de3396802f_SiteId=a19f121d-81e1-4858-a9d8-736e267fd4c7; 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charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: JmsCVQduf9uChswmV0kuThTGiVd/V9eFYVWUmJkPcsDiWuT9VXSB0JDZsy/cZjABzOf2uLrBiUf1wPRnMgG7JUjlw6FuEiZrdehZUM0Hgs9X5SQQ/XUvMGHZT8x25GfmwHVwXDBUFNpbG5bR00ufoa0zGA2/WX4GrN0YtQan3PF8/CDLBP8CDfJBWnueRNSEvKyM1HAGyZIHrfodXFzWDkzCZT9DIHMzb+9QCBcKvQmGuUPdsxXpuEjX3Orr4gTR8m6EhsCPWYljxv1Iy55AScg2Wdy85ugdAlVYrgC/GDcpI7sTc4yqWROigJ7JoNb/nfXnkL6JLRwV/u5rvg3hncN2u9LF/c2gkLdU3DFbpOIXtkKZBWN4shiywdDKesz+b7xPwC82LLjV2eu7RRpTpV8vU1NH11MSwLo11q7rG10fvjZ/oiHr764XGNLVVcaMCu2l9UAo3PTmuL42LN4GKrWsGqckZWdYYcisc/sSsx/655bZDxufGoG1jOaOzBZ+yCqzzbDAzvBFY652EbpEFRUuAxILXyyalrU6ibiDOzEOmAV//qUdwo7TqxKEEEC6BWWslNclbpD/lSwqEdhEV5EcsIl3dct96GiS+pzNQtfj4YVq+gGhgau2aUUXXQqE X-OriginatorOrg: fujitsu.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: OSAPR01MB7182.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0ca99a70-939b-4883-6e77-08dc4e3741af X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Mar 2024 08:24:01.1827 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a19f121d-81e1-4858-a9d8-736e267fd4c7 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Me0vtP21fDE7xyLyIos+D0QV4aGW48x+m1BsHXYmGRJesYeHQ4CdS60DvS6bwaRFT8QaY506xxkYzu3rDEWOL3pmW/ES1G72yW3L8vi4WIw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY3PR01MB10013 Dan Williams wrote: > Kobayashi,Daisuke wrote: > > Hello. > > > > This patch series adds a feature that displays the link status > > of the CXL1.1 device. >=20 > Good write up! One minor feedback going forward is to drop usage of > "This patch" in a description as that is self evident. >=20 > > CXL devices are extensions of PCIe. Therefore, from CXL2.0 onwards, > > the link status can be output in the same way as traditional PCIe. > > However, unlike devices from CXL2.0 onwards, CXL1.1 requires a > > different method to obtain the link status from traditional PCIe. > > This is because the link status of the CXL1.1 device is not mapped > > in the configuration space (as per cxl3.0 specification 8.1). > > Instead, the configuration space containing the link status is mapped > > to the memory mapped register region (as per cxl3.0 specification 8.2, > > Table 8-18). Therefore, the current lspci has a problem where it does > > not display the link status of the CXL1.1 device. > > This patch solves these issues. >=20 > One common way to rewrite a "This patch..." sentence is in "imperative" > tense, so for example: >=20 > "Solve these issues with sysfs attributes to expose the status > registers hidden in the RCRB." >=20 > ...i.e. write the commit log as if the patch is commanding the code to > change. You can find some more notes about this here: >=20 > https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#patch- > submission-notes >=20 > ...but really, this cover letter is higher quality than most, so thanks > for that! >=20 Thank you for your kind feedback. In the updated patch, I will revise the text and submit it. > > Kobayashi,Daisuke (3): > > Add sysfs attribute for CXL 1.1 device link status > > Remove conditional branch that is not suitable for cxl1.1 devices > > > > drivers/cxl/acpi.c | 4 - > > drivers/cxl/pci.c | 193 > +++++++++++++++++++++++++++++++++++++++++++++ > > 2 files changed, 193 insertions(+), 4 deletions(-) > > > > Add function to display cxl1.1 device link status > > > > lib/access.c | 29 +++++++++++++++++++++ > > lib/pci.h | 2 ++ > > ls-caps.c | 73 > ++++++++++++++++++++++++++++++++++++++++++++++++ > ++++ > > 3 files changed, 104 insertions(+) >=20 > The typical way I handle cases where I am updating the kernel side and > the user tooling side of a problem is to post the kernel changes and > then separately post the user changes with a lore link to the kernel > submission. >=20 > For PCI utils I believe you will need to send a separate pull request > via github once the kernel changes are accepted. I understand that it=1B$B!G=1B(Bs better to post separately.=20 After the changes to the kernel are accepted, I will submit a patch to pciu= tils.