From: Vinod Koul <vkoul@kernel.org>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: lpieralisi@kernel.org, robh@kernel.org, kw@linux.com,
bhelgaas@google.com, thierry.reding@gmail.com,
jonathanh@nvidia.com, kishon@ti.com, mani@kernel.org,
Sergey.Semin@baikalelectronics.ru, ffclaire1224@gmail.com,
linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com
Subject: Re: [PATCH V3 08/21] phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration
Date: Fri, 28 Oct 2022 17:43:21 +0530 [thread overview]
Message-ID: <Y1vHYduw4CQl5ssA@matsya> (raw)
In-Reply-To: <20221013183854.21087-9-vidyas@nvidia.com>
On 14-10-22, 00:08, Vidya Sagar wrote:
> Set ENABLE_L2_EXIT_RATE_CHANGE register bit to request UPHY PLL rate change
> to Gen1 during initialization. This helps in the below surprise link down
> cases,
> - Surprise link down happens at Gen3/Gen4 link speed.
> - Surprise link down happens and external REFCLK is cut off, which causes
> UPHY PLL rate to deviate to an invalid rate.
Applied, thanks
--
~Vinod
next prev parent reply other threads:[~2022-10-28 12:13 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-13 18:38 [PATCH V3 00/21] Enhancements to pcie-tegra194 driver Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 01/21] PCI: tegra194: Use devm_gpiod_get_optional() to parse "nvidia,refclk-select" Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 02/21] PCI: tegra194: Drive CLKREQ signal low explicitly Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 03/21] PCI: tegra194: Fix polling delay for L2 state Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 04/21] PCI: tegra194: Handle errors in BPMP response Vidya Sagar
2023-01-13 15:15 ` Lorenzo Pieralisi
2022-10-13 18:38 ` [PATCH V3 05/21] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 06/21] PCI: tegra194: Refactor LTSSM state polling on surprise down Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 07/21] PCI: tegra194: Disable direct speed change for EP Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 08/21] phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration Vidya Sagar
2022-10-28 11:42 ` Vinod Koul
2022-10-28 11:49 ` Vidya Sagar
2022-10-28 12:13 ` Vinod Koul [this message]
2022-10-13 18:38 ` [PATCH V3 09/21] PCI: tegra194: Calibrate P2U for endpoint mode Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 10/21] PCI: tegra194: Free resources during controller deinitialization Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 11/21] PCI: tegra194: Remove IRQF_ONESHOT flag during Endpoint interrupt registration Vidya Sagar
2022-11-14 11:56 ` Lorenzo Pieralisi
2023-01-13 15:21 ` Lorenzo Pieralisi
2022-10-13 18:38 ` [PATCH V3 12/21] PCI: tegra194: Enable DMA interrupt Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 13/21] PCI: tegra194: Enable hardware hot reset mode in Endpoint Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 14/21] PCI: tegra194: Allow system suspend when the Endpoint link is not up Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 15/21] PCI: tegra194: Disable L1.2 capability of Tegra234 EP Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 16/21] PCI: tegra194: Set LTR message request before PCIe link up Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 17/21] PCI: tegra194: Reduce AXI slave timeout value Vidya Sagar
2023-01-13 15:31 ` Lorenzo Pieralisi
2022-10-13 18:38 ` [PATCH V3 18/21] PCI: tegra194: Don't force the device into the D0 state before L2 Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 19/21] PCI: tegra194: Free up EP resources during remove() Vidya Sagar
2023-01-13 15:28 ` Lorenzo Pieralisi
2022-10-13 18:38 ` [PATCH V3 20/21] dt-bindings: PCI: tegra194: Add monitor clock support Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 21/21] PCI: tegra194: Add core " Vidya Sagar
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