From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: robh@kernel.org, kw@linux.com, bhelgaas@google.com,
thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com,
vkoul@kernel.org, mani@kernel.org,
Sergey.Semin@baikalelectronics.ru, ffclaire1224@gmail.com,
linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com
Subject: Re: [PATCH V3 04/21] PCI: tegra194: Handle errors in BPMP response
Date: Fri, 13 Jan 2023 16:15:34 +0100 [thread overview]
Message-ID: <Y8F1ljVyVST+aSu4@lpieralisi> (raw)
In-Reply-To: <20221013183854.21087-5-vidyas@nvidia.com>
On Fri, Oct 14, 2022 at 12:08:37AM +0530, Vidya Sagar wrote:
> The return value from tegra_bpmp_transfer indicates the success or
> failure of the IPC transaction with BPMP. If the transaction
> succeeded, we also need to check the actual command's result code.
> Add code to do this.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> V3:
> * None
>
> V2:
> * None
>
> drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 685aee378c93..ae7e0d8f693b 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1260,6 +1260,7 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
> struct mrq_uphy_response resp;
> struct tegra_bpmp_message msg;
> struct mrq_uphy_request req;
> + int err;
>
> /*
> * Controller-5 doesn't need to have its state set by BPMP-FW in
> @@ -1282,7 +1283,13 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
> msg.rx.data = &resp;
> msg.rx.size = sizeof(resp);
>
> - return tegra_bpmp_transfer(pcie->bpmp, &msg);
> + err = tegra_bpmp_transfer(pcie->bpmp, &msg);
> + if (err)
> + return err;
> + if (msg.rx.ret)
> + return -EINVAL;
> +
> + return 0;
> }
>
> static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
> @@ -1291,6 +1298,7 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
> struct mrq_uphy_response resp;
> struct tegra_bpmp_message msg;
> struct mrq_uphy_request req;
> + int err;
>
> memset(&req, 0, sizeof(req));
> memset(&resp, 0, sizeof(resp));
> @@ -1310,7 +1318,13 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
> msg.rx.data = &resp;
> msg.rx.size = sizeof(resp);
>
> - return tegra_bpmp_transfer(pcie->bpmp, &msg);
> + err = tegra_bpmp_transfer(pcie->bpmp, &msg);
> + if (err)
> + return err;
> + if (msg.rx.ret)
> + return -EINVAL;
I wonder whether you can embed the return value check within
the function itself.
Lorenzo
> +
> + return 0;
> }
>
> static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
> --
> 2.17.1
>
>
> --
> linux-phy mailing list
> linux-phy@lists.infradead.org
> https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2023-01-13 15:24 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-13 18:38 [PATCH V3 00/21] Enhancements to pcie-tegra194 driver Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 01/21] PCI: tegra194: Use devm_gpiod_get_optional() to parse "nvidia,refclk-select" Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 02/21] PCI: tegra194: Drive CLKREQ signal low explicitly Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 03/21] PCI: tegra194: Fix polling delay for L2 state Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 04/21] PCI: tegra194: Handle errors in BPMP response Vidya Sagar
2023-01-13 15:15 ` Lorenzo Pieralisi [this message]
2022-10-13 18:38 ` [PATCH V3 05/21] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 06/21] PCI: tegra194: Refactor LTSSM state polling on surprise down Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 07/21] PCI: tegra194: Disable direct speed change for EP Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 08/21] phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration Vidya Sagar
2022-10-28 11:42 ` Vinod Koul
2022-10-28 11:49 ` Vidya Sagar
2022-10-28 12:13 ` Vinod Koul
2022-10-13 18:38 ` [PATCH V3 09/21] PCI: tegra194: Calibrate P2U for endpoint mode Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 10/21] PCI: tegra194: Free resources during controller deinitialization Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 11/21] PCI: tegra194: Remove IRQF_ONESHOT flag during Endpoint interrupt registration Vidya Sagar
2022-11-14 11:56 ` Lorenzo Pieralisi
2023-01-13 15:21 ` Lorenzo Pieralisi
2022-10-13 18:38 ` [PATCH V3 12/21] PCI: tegra194: Enable DMA interrupt Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 13/21] PCI: tegra194: Enable hardware hot reset mode in Endpoint Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 14/21] PCI: tegra194: Allow system suspend when the Endpoint link is not up Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 15/21] PCI: tegra194: Disable L1.2 capability of Tegra234 EP Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 16/21] PCI: tegra194: Set LTR message request before PCIe link up Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 17/21] PCI: tegra194: Reduce AXI slave timeout value Vidya Sagar
2023-01-13 15:31 ` Lorenzo Pieralisi
2022-10-13 18:38 ` [PATCH V3 18/21] PCI: tegra194: Don't force the device into the D0 state before L2 Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 19/21] PCI: tegra194: Free up EP resources during remove() Vidya Sagar
2023-01-13 15:28 ` Lorenzo Pieralisi
2022-10-13 18:38 ` [PATCH V3 20/21] dt-bindings: PCI: tegra194: Add monitor clock support Vidya Sagar
2022-10-13 18:38 ` [PATCH V3 21/21] PCI: tegra194: Add core " Vidya Sagar
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