From: Niklas Cassel <Niklas.Cassel@wdc.com>
To: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
Damien Le Moal <damien.lemoal@opensource.wdc.com>,
Bjorn Helgaas <bhelgaas@google.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
Mario Limonciello <mario.limonciello@amd.com>,
Brijesh Singh <brijesh.singh@amd.com>
Subject: Re: [PATCH] pci: Avoid FLR for AMD FCH AHCI adapters
Date: Mon, 30 Jan 2023 16:33:59 +0000 [thread overview]
Message-ID: <Y9fxdvDg33oAFT7A@x1-carbon> (raw)
In-Reply-To: <6bcf0e30-8a33-dbe5-415b-593f916f0fa5@amd.com>
On Mon, Jan 30, 2023 at 09:42:36PM +0530, Shyam Sundar S K wrote:
>
>
> On 1/30/2023 8:51 PM, Bjorn Helgaas wrote:
> > [+cc Mario, Shyam, Brijesh]
> >
> > On Sat, Jan 28, 2023 at 10:39:51AM +0900, Damien Le Moal wrote:
> >> PCI passthrough to VMs does not work with AMD FCH AHCI adapters: the
> >> guest OS fails to correctly probe devices attached to the controller due
> >> to FIS communication failures.
> >
> > What does a FIS communication failure look like? Can we include a
> > line or two of dmesg output here to help users find this fix?
> >
> > AMD folks: Can you confirm/deny that this is a hardware erratum in
> > this device? Do you know of any other devices that need a similar
> > workaround?
>
> Niklas, can you send the list of AHCI device id present on your system?
> perhaps a lspci output?
Of course, here you go:
# lspci -vvvnns 49:00.0
49:00.0 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51) (prog-if 01 [AHCI 1.0])
Subsystem: Super Micro Computer Inc H12SSL-i [15d9:7901]
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 76
IOMMU group: 48
Region 5: Memory at b1500000 (32-bit, non-prefetchable) [size=2K]
Capabilities: [48] Vendor Specific Information: Len=08 <?>
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [64] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0W
DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset-
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 16GT/s, Width x16, ASPM L0s L1, Exit Latency L0s <64ns, L1 <1us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 16GT/s, Width x16
TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR-
10BitTagComp+ 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
FRS- TPHComp- ExtTPHComp-
AtomicOpsCap: 32bit- 64bit- 128bitCAS-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- 10BitTagReq- OBFF Disabled,
AtomicOpsCtl: ReqEn-
LnkCap2: Supported Link Speeds: 2.5-16GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
LnkCtl2: Target Link Speed: 16GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
Retimer- 2Retimers- CrosslinkRes: unsupported
Capabilities: [a0] MSI: Enable+ Count=16/16 Maskable- 64bit+
Address: 00000000fee00000 Data: 0000
Capabilities: [d0] SATA HBA v1.0 InCfgSpace
Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
Capabilities: [150 v2] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn-
MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
HeaderLog: 00000000 00000000 00000000 00000000
Capabilities: [270 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: 0
Capabilities: [2a0 v1] Access Control Services
ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
Capabilities: [400 v1] Data Link Feature <?>
Capabilities: [410 v1] Physical Layer 16.0 GT/s <?>
Capabilities: [440 v1] Lane Margining at the Receiver <?>
Kernel driver in use: ahci
Kind regards,
Niklas
prev parent reply other threads:[~2023-01-30 16:34 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-28 1:39 [PATCH] pci: Avoid FLR for AMD FCH AHCI adapters Damien Le Moal
2023-01-30 15:21 ` Bjorn Helgaas
2023-01-30 15:46 ` Niklas Cassel
2023-01-30 16:04 ` Bjorn Helgaas
2023-01-31 0:36 ` Damien Le Moal
2023-01-30 16:12 ` Shyam Sundar S K
2023-01-30 16:33 ` Niklas Cassel [this message]
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