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Sun, 13 Mar 2022 10:06:40 -0700 (PDT) Received: from builder.lan ([2600:1700:a0:3dc8:3697:f6ff:fe85:aac9]) by smtp.gmail.com with ESMTPSA id p21-20020a4a2f15000000b00320fca09b74sm6326576oop.1.2022.03.13.10.06.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 10:06:40 -0700 (PDT) Date: Sun, 13 Mar 2022 12:06:38 -0500 From: Bjorn Andersson To: Dmitry Baryshkov Cc: Andy Gross , Stephen Boyd , Michael Turquette , Taniya Das , Lorenzo Pieralisi , Krzysztof Wilczy??ski , Bjorn Helgaas , Prasad Malisetty , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [RFC PATCH 4/5] PCI: qcom: Remove unnecessary pipe_clk handling Message-ID: References: <20220313000824.229405-1-dmitry.baryshkov@linaro.org> <20220313000824.229405-5-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220313000824.229405-5-dmitry.baryshkov@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Sat 12 Mar 18:08 CST 2022, Dmitry Baryshkov wrote: > QMP PHY driver already does clk_prepare_enable()/_disable() pipe_clk. > Remove extra calls to enable/disable this clock from the PCIe driver, so > that the PHY driver can manage the clock on its own. > > Fixes: aa9c0df98c29 ("PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280") > Cc: Prasad Malisetty > Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > drivers/pci/controller/dwc/pcie-qcom.c | 50 ++------------------------ > 1 file changed, 3 insertions(+), 47 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 6ab90891801d..a6becafb6a77 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -128,7 +128,6 @@ struct qcom_pcie_resources_2_3_2 { > struct clk *master_clk; > struct clk *slave_clk; > struct clk *cfg_clk; > - struct clk *pipe_clk; > struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; > }; > > @@ -165,7 +164,6 @@ struct qcom_pcie_resources_2_7_0 { > int num_clks; > struct regulator_bulk_data supplies[2]; > struct reset_control *pci_reset; > - struct clk *pipe_clk; > struct clk *pipe_clk_src; > struct clk *phy_pipe_clk; > struct clk *ref_clk_src; > @@ -597,8 +595,7 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) > if (IS_ERR(res->slave_clk)) > return PTR_ERR(res->slave_clk); > > - res->pipe_clk = devm_clk_get(dev, "pipe"); > - return PTR_ERR_OR_ZERO(res->pipe_clk); > + return 0; > } > > static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) > @@ -613,13 +610,6 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) > regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); > } > > -static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie) > -{ > - struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; > - > - clk_disable_unprepare(res->pipe_clk); > -} > - > static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) > { > struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; > @@ -694,22 +684,6 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) > return ret; > } > > -static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) > -{ > - struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; > - struct dw_pcie *pci = pcie->pci; > - struct device *dev = pci->dev; > - int ret; > - > - ret = clk_prepare_enable(res->pipe_clk); > - if (ret) { > - dev_err(dev, "cannot prepare/enable pipe clock\n"); > - return ret; > - } > - > - return 0; > -} > - > static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) > { > struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; > @@ -1198,8 +1172,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) > return PTR_ERR(res->ref_clk_src); > } > > - res->pipe_clk = devm_clk_get(dev, "pipe"); > - return PTR_ERR_OR_ZERO(res->pipe_clk); > + return 0; > } > > static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > @@ -1238,12 +1211,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > goto err_disable_clocks; > } > > - ret = clk_prepare_enable(res->pipe_clk); > - if (ret) { > - dev_err(dev, "cannot prepare/enable pipe clock\n"); > - goto err_disable_clocks; > - } > - > /* Wait for reset to complete, required on SM8450 */ > usleep_range(1000, 1500); > > @@ -1298,14 +1265,7 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) > if (pcie->cfg->pipe_clk_need_muxing) > clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); > > - return clk_prepare_enable(res->pipe_clk); > -} > - > -static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) > -{ > - struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; > - > - clk_disable_unprepare(res->pipe_clk); > + return 0; > } > > static int qcom_pcie_link_up(struct dw_pcie *pci) > @@ -1455,9 +1415,7 @@ static const struct qcom_pcie_ops ops_1_0_0 = { > static const struct qcom_pcie_ops ops_2_3_2 = { > .get_resources = qcom_pcie_get_resources_2_3_2, > .init = qcom_pcie_init_2_3_2, > - .post_init = qcom_pcie_post_init_2_3_2, > .deinit = qcom_pcie_deinit_2_3_2, > - .post_deinit = qcom_pcie_post_deinit_2_3_2, > .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > }; > > @@ -1484,7 +1442,6 @@ static const struct qcom_pcie_ops ops_2_7_0 = { > .deinit = qcom_pcie_deinit_2_7_0, > .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > .post_init = qcom_pcie_post_init_2_7_0, > - .post_deinit = qcom_pcie_post_deinit_2_7_0, > }; > > /* Qcom IP rev.: 1.9.0 */ > @@ -1494,7 +1451,6 @@ static const struct qcom_pcie_ops ops_1_9_0 = { > .deinit = qcom_pcie_deinit_2_7_0, > .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > .post_init = qcom_pcie_post_init_2_7_0, > - .post_deinit = qcom_pcie_post_deinit_2_7_0, > .config_sid = qcom_pcie_config_sid_sm8250, > }; > > -- > 2.34.1 >