Re: [PATCH] PCI: Quirk Intel DG2 ASPM L1 acceptable latency to be unlimited

[Mika Westerberg <mika.westerberg@linux.intel.com>]

On Thu, Apr 07, 2022 at 12:06:55PM -0500, Bjorn Helgaas wrote:
> On Tue, Apr 05, 2022 at 12:38:10PM +0300, Mika Westerberg wrote:
> > Intel DG2 discrete graphics PCIe endpoints hard-code their acceptable L1
> > ASPM latency to be < 1us even though the hardware actually supports
> > higher latencies (> 64 us) just fine. In order to allow the links to go
> > into L1 and save power, quirk the acceptable L1 ASPM latency for these
> > endpoints to be unlimited.
> > 
> > Note this does not have any effect unless the user requested the kernel
> > to enable ASPM in the first place (by default we don't enable it). This
> > is done with "pcie_aspm=force pcie_aspm.policy=powersupsersave" command
> > line parameters.
> > 
> > Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> 
> I wordsmithed as below and applied to pci/aspm for v5.19, thanks!

Thanks!

> Please double-check that I didn't screw up the FIELD_GET/PREP usage.

Looks good to me. I did not even know we have such macros, thanks for
pointing that out :)