From: Johan Hovold <johan@kernel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
Vinod Koul <vkoul@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Rob Herring <robh@kernel.org>
Subject: Re: [PATCH v15 5/7] dt-bindings: PCI: qcom: Support additional MSI interrupts
Date: Wed, 29 Jun 2022 16:21:05 +0200 [thread overview]
Message-ID: <Yrxf0QANRAeLCVAU@hovoldconsulting.com> (raw)
In-Reply-To: <20220620112015.1600380-6-dmitry.baryshkov@linaro.org>
On Mon, Jun 20, 2022 at 02:20:13PM +0300, Dmitry Baryshkov wrote:
> On Qualcomm platforms each group of 32 MSI vectors is routed to the
> separate GIC interrupt. Document mapping of additional interrupts.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../devicetree/bindings/pci/qcom,pcie.yaml | 51 +++++++++++++++++--
> 1 file changed, 48 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 0b69b12b849e..7e84063afe25 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -43,11 +43,12 @@ properties:
> maxItems: 5
>
> interrupts:
> - maxItems: 1
> + minItems: 1
> + maxItems: 8
>
> interrupt-names:
> - items:
> - - const: msi
> + minItems: 1
> + maxItems: 8
>
> # Common definitions for clocks, clock-names and reset.
> # Platform constraints are described later.
> @@ -623,6 +624,50 @@ allOf:
> - resets
> - reset-names
>
> + # On newer chipsets support either 1 or 8 msi interrupts
> + # On older chipsets it's always 1 msi interrupt
> + - if:
> + properties:
> + compatibles:
This conditional always evaluates to false due to the typo in the
property name here (plural "compatibles").
I've just posted a fix for this (and another bug just like it) as part
of a series that depends on this series:
https://lore.kernel.org/all/20220629141000.18111-1-johan+linaro@kernel.org/
Not sure if you need to respin a v16 just for this but otherwise it
could be folded in here.
> + contains:
> + enum:
> + - qcom,pcie-msm8996
> + - qcom,pcie-sc7280
> + - qcom,pcie-sc8180x
> + - qcom,pcie-sdm845
> + - qcom,pcie-sm8150
> + - qcom,pcie-sm8250
> + - qcom,pcie-sm8450-pcie0
> + - qcom,pcie-sm8450-pcie1
> + then:
> + oneOf:
> + - properties:
> + interrupts:
> + maxItems: 1
> + interrupt-names:
> + items:
> + - const: msi
> + - properties:
> + interrupts:
> + minItems: 8
> + interrupt-names:
> + items:
> + - const: msi0
> + - const: msi1
> + - const: msi2
> + - const: msi3
> + - const: msi4
> + - const: msi5
> + - const: msi6
> + - const: msi7
> + else:
> + properties:
> + interrupts:
> + maxItems: 1
> + interrupt-names:
> + items:
> + - const: msi
> +
> unevaluatedProperties: false
>
> examples:
Johan
next prev parent reply other threads:[~2022-06-29 14:21 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-20 11:20 [PATCH v15 0/7] PCI: dwc: Fix higher MSI vectors handling Dmitry Baryshkov
2022-06-20 11:20 ` [PATCH v15 1/7] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Dmitry Baryshkov
2022-06-29 14:23 ` Johan Hovold
2022-06-20 11:20 ` [PATCH v15 2/7] PCI: dwc: Convert msi_irq to the array Dmitry Baryshkov
2022-06-29 14:23 ` Johan Hovold
2022-06-20 11:20 ` [PATCH v15 3/7] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Dmitry Baryshkov
2022-06-29 14:24 ` Johan Hovold
2022-06-20 11:20 ` [PATCH v15 4/7] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
2022-06-29 14:24 ` Johan Hovold
2022-06-20 11:20 ` [PATCH v15 5/7] dt-bindings: PCI: qcom: Support additional MSI interrupts Dmitry Baryshkov
2022-06-29 14:21 ` Johan Hovold [this message]
2022-06-20 11:20 ` [PATCH v15 6/7] arm64: dts: qcom: sm8250: provide " Dmitry Baryshkov
2022-06-20 11:20 ` [PATCH v15 7/7] PCI: qcom: Revert "PCI: qcom: Add support for handling MSIs from 8 endpoints" Dmitry Baryshkov
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