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[34.168.215.201]) by smtp.gmail.com with ESMTPSA id v66-20020a622f45000000b00536f0370db8sm7172457pfv.212.2022.08.29.11.08.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 11:08:51 -0700 (PDT) Date: Mon, 29 Aug 2022 18:08:47 +0000 From: William McVicker To: Bjorn Helgaas Cc: kernel-team@android.com, Sajid Dalvi , Matthias Kaehlcke , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] PCI/PM: Switch D3Hot delay to also use usleep_range Message-ID: References: <20220817230821.47048-1-willmcvicker@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220817230821.47048-1-willmcvicker@google.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 08/17/2022, Will McVicker wrote: > From: Sajid Dalvi > > Since the PCI spec requires a 10ms D3Hot delay (defined by > PCI_PM_D3HOT_WAIT) and a few of the PCI quirks update the D3Hot delay up > to 120ms, let's add support for both usleep_range and msleep based on > the delay time to improve the delay accuracy. > > This patch is based off of a commit from Sajid Dalvi > in the Pixel 6 kernel tree [1]. Testing on a Pixel 6, found that the > 10ms delay for the Exynos PCIe device was on average delaying for 19ms > when the spec requires 10ms. Switching from msleep to uslseep_range > therefore decreases the resume time on a Pixel 6 on average by 9ms. > > [1] https://android.googlesource.com/kernel/gs/+/18a8cad68d8e6d50f339a716a18295e6d987cee3 > > Signed-off-by: Sajid Dalvi > Signed-off-by: Will McVicker > --- > drivers/pci/pci.c | 16 +++++++++++----- > 1 file changed, 11 insertions(+), 5 deletions(-) > > v3: > * Use DIV_ROUND_CLOSEST instead of bit manipulation. > * Minor refactor to use max() where relavant. > > v2: > * Update to use 20-25% upper bound > * Update to use usleep_range() for <=20ms, else use msleep() > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 95bc329e74c0..cfa8386314f2 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -66,13 +66,19 @@ struct pci_pme_device { > > static void pci_dev_d3_sleep(struct pci_dev *dev) > { > - unsigned int delay = dev->d3hot_delay; > + unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay); > > - if (delay < pci_pm_d3hot_delay) > - delay = pci_pm_d3hot_delay; > + if (delay_ms) { > + if (delay_ms <= 20) { > + /* Use a 20% upper bound with 1ms minimum */ > + unsigned int upper = max(DIV_ROUND_CLOSEST(delay_ms, 5), 1U); > > - if (delay) > - msleep(delay); > + usleep_range(delay_ms * USEC_PER_MSEC, > + (delay_ms + upper) * USEC_PER_MSEC); > + } else { > + msleep(delay_ms); > + } > + } > } > > bool pci_reset_supported(struct pci_dev *dev) > > base-commit: 274a2eebf80c60246f9edd6ef8e9a095ad121264 > -- > 2.37.1.595.g718a3a8f04-goog > Hi Bjorn, I'm just checking up on this patch in case it got lost in your inbox. Please take a look and let me know if you have any concerns. And thanks again for the reviews Matthias! Regards, Will