From: "Krzysztof Wilczyński" <kw@linux.com>
To: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Russell Currey <ruscur@russell.cc>,
oohall@gmail.com, Paul Menzel <pmenzel@molgen.mpg.de>,
Lukas Wunner <lukas@wunner.de>,
linux-pci@vger.kernel.org, Sasha Levin <sashal@kernel.org>
Subject: Re: [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports
Date: Mon, 22 Aug 2022 12:43:44 +0900 [thread overview]
Message-ID: <YwL7cOM0o/VA+e6l@rocinante> (raw)
In-Reply-To: <20220816102042.69125-1-mika.westerberg@linux.intel.com>
[Adding Sasha for visibility]
Hi Mika,
> There is a BIOS bug on Intel Tiger Lake and Alder Lake systems that
> accidentally clears the root port PIO log size even though it should be 4.
> Fix the affected root ports by forcing the log size to be 4 if it is set
> to 0. The BIOS for the next generation CPUs should have this fixed.
Thank you for the fix!
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=209943
I've added Sasha, as there is probably a lot of the 11th and 12th
generation of Intel hardware out there that might warrant a backport
to stable kernels.
Krzysztof
next prev parent reply other threads:[~2022-08-22 3:43 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-16 10:20 [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports Mika Westerberg
2022-08-22 3:18 ` Sathyanarayanan Kuppuswamy
2022-08-22 3:19 ` Sathyanarayanan Kuppuswamy
2022-08-22 3:43 ` Krzysztof Wilczyński [this message]
2022-09-27 22:40 ` Bjorn Helgaas
2022-09-27 23:13 ` Bjorn Helgaas
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