Re: DWC PCIe endpoint iATU vs BAR MASK ordering

[Niklas Cassel <cassel@kernel.org>]

On Wed, Nov 20, 2024 at 12:37:17PM -0500, Frank Li wrote:
> Maybe off topic, I think if support combine some segmement address to
> one bar should be wonderful, such as combine MSI ITS address and other
> register to BAR0. It is not worth to waste one bar, which just for
> doorbell.

I was thinking about this as well.

If we want a single BAR to redirect to two different physical memory areas,
then we can no longer use BAR Match Mode.

Sure, we could use two different iATUs and use Address Match Mode.
However, the problem is that the minimum size of an Address Translation
Region (CX_ATU_MIN_REGION_SIZE). E.g. on rk3588 CX_ATU_MIN_REGION_SIZE
is 64k...

So we would need to split the BAR in chunks of CX_ATU_MIN_REGION_SIZE.

If we look at e.g. the NVMe doorbells in BAR0, they are defined to
start at offset 0x1000 (4k).
See "Figure 4: PCI Express Specific Controller Property Definitions" in:
https://nvmexpress.org/wp-content/uploads/NVM-Express-PCI-Express-Transport-Specification-Revision-1.1-2024.08.05-Ratified.pdf

So, since that fixed offset is smaller than CX_ATU_MIN_REGION_SIZE,
we are out of luck... (at least for rk3588).

But.. perhaps the idea is still worth it?
For controllers that have CX_ATU_MIN_REGION_SIZE == 4k,
they could use one iATU for offset 0x-0xfff, and
another iATU for 0x1000-0x1fff.

(And of course, NVMe is just one specification out of many...)

I have no idea how CX_ATU_MIN_REGION_SIZE is set on NXP DWC PCIe
controllers.


Kind regards,
Niklas