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Mon, 23 Dec 2024 07:50:07 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BN7o6Nm027292 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 23 Dec 2024 07:50:06 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 22 Dec 2024 23:50:00 -0800 Date: Mon, 23 Dec 2024 13:19:57 +0530 From: Varadarajan Narayanan To: Krzysztof Kozlowski CC: , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v3 1/5] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy Message-ID: References: <20241217100359.4017214-1-quic_varada@quicinc.com> <20241217100359.4017214-2-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: G7LY8sYViYMibK_Ix7Wj0HgbzslH0iz9 X-Proofpoint-GUID: G7LY8sYViYMibK_Ix7Wj0HgbzslH0iz9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 adultscore=0 mlxlogscore=999 clxscore=1015 suspectscore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412230068 On Wed, Dec 18, 2024 at 11:28:18AM +0100, Krzysztof Kozlowski wrote: > On Tue, Dec 17, 2024 at 03:33:55PM +0530, Varadarajan Narayanan wrote: > > From: Nitheesh Sekar > > > > Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332. > > > > Signed-off-by: Nitheesh Sekar > > Signed-off-by: Varadarajan Narayanan > > --- > > v3: Fix compatible string to be similar to other phys and rename file accordingly > > Fix clocks minItems -> maxItems > > I think there was just one clock, so you increased it to two. IPQ5018 patch series had one clock. IPQ5332 introduced additional clocks and it became four. Of the four clocks, two were NoC related clocks. Since the NoC clocks are handled in icc-clk based interconnect driver, have dropped those two and have incldued the two here. > > Change one of the maintainer from Sricharan to Varadarajan > > > > v2: Rename the file to match the compatible > > Drop 'driver' from title > > Dropped 'clock-names' > > Fixed 'reset-names' > > -- > > .../phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 82 +++++++++++++++++++ > > 1 file changed, 82 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml > > > > diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml > > new file mode 100644 > > index 000000000000..0634d4fb85d1 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml > > @@ -0,0 +1,82 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Qualcomm UNIPHY PCIe 28LP PHY > > + > > +maintainers: > > + - Nitheesh Sekar > > + - Varadarajan Narayanan > > + > > +description: > > + PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC > > + > > +properties: > > + compatible: > > + enum: > > + - qcom,ipq5332-uniphy-gen3x1-pcie-phy > > + - qcom,ipq5332-uniphy-gen3x2-pcie-phy > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 2 > > I should have been more specific last time, but I assumed you will take > other bindings as example. well, so now proper review: you need to list > tiems. Sure. > > + > > + resets: > > + minItems: 2 > > + maxItems: 3 > > No answer to my previous question. Question stands. I assume this question:- "So where are three items?" [1] Will remove this and list the items. > > + > > + reset-names: > > + minItems: 2 > > + items: > > + - const: phy > > + - const: phy_ahb > > + - const: phy_cfg > > + > > + "#phy-cells": > > + const: 0 > > + > > + "#clock-cells": > > + const: 0 > > + > > + clock-output-names: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - resets > > + - reset-names > > + - clocks > > Keep the same order as in properties block. Ok. Thanks Varada 1. https://lore.kernel.org/linux-arm-msm/c685ca4e-3992-4deb-adfb-da3bbcb59685@linaro.org/