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Thu, 02 Jan 2025 17:43:28 -0800 (PST) Received: from localhost ([2a00:79e0:2e14:7:2f1b:db40:bb38:fa8e]) by smtp.gmail.com with UTF8SMTPSA id 98e67ed59e1d1-2f4477c84d0sm27287665a91.14.2025.01.02.17.43.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Jan 2025 17:43:27 -0800 (PST) Date: Thu, 2 Jan 2025 17:43:26 -0800 From: Brian Norris To: Manivannan Sadhasivam Cc: Jingoo Han , Lorenzo Pieralisi , Bjorn Helgaas , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Rob Herring , Marc Zyngier , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= Subject: Re: [PATCH] PCI: dwc: Use level-triggered handler for MSI IRQs Message-ID: References: <20241015141215.1.Id60295bee6aacf44aa3664e702012cb4710529c3@changeid> <20241230171145.hsqynixmowjn77ki@thinkpad> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241230171145.hsqynixmowjn77ki@thinkpad> On Mon, Dec 30, 2024 at 10:41:45PM +0530, Manivannan Sadhasivam wrote: > On Tue, Oct 15, 2024 at 02:12:16PM -0700, Brian Norris wrote: > > From: Brian Norris > > > > Per Synopsis's documentation, the msi_ctrl_int signal is > > level-triggered, not edge-triggered. > > > > Could you please quote the spec reference? >From the reference manual for msi_ctrl_int: "Asserted when an MSI interrupt is pending. De-asserted when there is no MSI interrupt pending. ... Active State: High (level)" The reference manual also points at the databook for more info. One relevant excerpt from the databook: "When any status bit remains set, then msi_ctrl_int remains asserted. The interrupt status register provides a status bit for up to 32 interrupt vectors per Endpoint. When the decoded interrupt vector is enabled but is masked, then the controller sets the corresponding bit in interrupt status register but the it does not assert the top-level controller output msi_ctrl_int. That's essentially a prose description of level-triggering, plus 32-vector multiplexing and masking. Did you want a v2 with this included, or did you just want it noted here? (Side note: I think it doesn't really matter that much whether we use the 'level' or 'edge' variant handlers here, at least if the parent interrupt is configured correctly as level-triggered. We're not actually in danger of a level-triggered interrupt flood or similar issue.) Brian