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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?J0aYd8TIKAI3VL9miyOxJFii5/wFdo7kv0/77NScezhdoK6QNBoqrNXNSMI0?= =?us-ascii?Q?Z9k/iuEMapHr4UHtR/mhB4Sx5xeF6upQqDDPWGdicZqZ/btAgursHyZCJV9f?= =?us-ascii?Q?vbj5TmnTon89NgshkAG6dHSmLLkdVgckV7z+11JrS71cx+UZoWSgowbetwMx?= =?us-ascii?Q?bbLS5I+iRXH6Gs0RobIFUL1LWRoxmXxBM/0qYZFatHrXIyUNOsctG5jGzfhp?= =?us-ascii?Q?ScaLe/klDfYIafJnLkcXsvrSv4/VL9velJNDMCtbAaEizB/5iDZbxdddoLst?= =?us-ascii?Q?gh/MsPcJJm2VezncivRrz07omzQVXi3mfggIP/KQQ0Dwci2qCI2hEaL9F0Uu?= =?us-ascii?Q?3ZKFCDU1iuHCFr2tqRLDzBiU1vngG+QYNF61PrgH0gf3PckAxbJbDxHnaua1?= =?us-ascii?Q?/uyPAdEEWUBHVsUDknDAOS//MWPW1Xc94ViTXAYPdhfQFFc3EhdSGRFQJ0Kp?= =?us-ascii?Q?FzXGuzikLYQvNvE+gQ2m+pjXCg8nXi8esV7vKa+WWx4oc/dfSxSSjAOQjifB?= =?us-ascii?Q?+P9c39IBxeISixRLDReg0QgTwwIOyTbjLuoBkhJ0hdHkYXeMFzBsDSgnBlr0?= =?us-ascii?Q?ywDc6Lxa7lEExaaoJ5VvSMhnrynshAYmxXwKJnv2/tlgII7XxIZjvJkXPJwp?= =?us-ascii?Q?X1IyPx8utwo+USYS3k3dE6wkwV2eC9m15ClTESy2FX8kzy9ikoMBnvtBLtRL?= =?us-ascii?Q?twhtnOWFQzTGI0mZSH8B0VgbRt7MW3g0sg0vXI+UPalboYAC0RhXTvToPBut?= =?us-ascii?Q?7Mxb77Lo2cbwcOtQaUBZhjoYKzM6hYv4heAj6iH5eyJPyVbetIqHO44ZMCtF?= =?us-ascii?Q?6iSSj9qJGP6aly7sek/11Bzl1QgsD4byWoDnU0YjeBhManEPa9bBefuHqlUV?= =?us-ascii?Q?HTmjZqjcft28DnQrwA+WtvS5/Rq66FWn9iW5cWb2JW+ZvmDmNx1NoKTK/MuR?= =?us-ascii?Q?T8ZEs5HnSfEUUBwiVcYFTIIU/58rCB1BaAN4a7aaN9LeUQCNk1FSGFXv5kDP?= =?us-ascii?Q?jX2Fowj6THoc1fsljPlOZqlgm1Yfu8NC7PLOXNCdEbQ5WyTVy46ae0DW0Phn?= =?us-ascii?Q?tHLTAZ7GbVKanQwR+4W0effFRATTrsMbx+4fmuKc4NykgSKT2rPHamRQmYrJ?= =?us-ascii?Q?9rOL4LTfDNDdJwcwVy/Y759wbJtqMz5oaEfkGO3Uaq91LwsH/AZQ2KuXuCuR?= =?us-ascii?Q?Kg+Fgopu4lMzSFs4WfnOto9N90xtNnZdm+/3kY69csdEFAlCOwCztplrtdgK?= =?us-ascii?Q?3VO+OV+pdDVR42AepMOx4F1iop6LFESMAoL/JzliqoSONMyXBNV5yOX+8eyW?= =?us-ascii?Q?AnNguXYEfabZi+48Z8HTLJBrXK3jh84OIOFW4CbBz2pTH0SD9PSYyF33eQiN?= =?us-ascii?Q?7iel/FvIP9AmOieBXw1kLZmC3euVWZCAhVu6r8kJIcxuNorUSk+3l7Pppe8B?= =?us-ascii?Q?UJiTIsn+LI5d6x4OYb03zw+FEw6xPeYDqrL+6QtSOvJPu8MqhaciGsTBeyCR?= =?us-ascii?Q?m3o2NeFVSyp/TfhcirMGIgsSiEak+qSQ0giOcgRw6CliFMceyXXfDdDOKkFl?= =?us-ascii?Q?hIyyUNyFDgEoqDRjJ60MlztbrxwpzfXVaxenS0P4?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: e7d6b5d5-a44f-4f83-3c20-08dd380a13b6 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jan 2025 21:50:08.8772 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BMqNMO9q4ri+p0vwE9jfVrMVgDNmhleeTmDNj+gf7qPYADGmmK13TmoYXPK2Gif3b6nrqYXv3pLSNtXpBehGXA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8509 On Sat, Jan 18, 2025 at 03:07:27PM -0600, Bjorn Helgaas wrote: > From: Bjorn Helgaas > > For readability, fix typos and comments that needlessly exceed 80 columns. > > Signed-off-by: Bjorn Helgaas Reviewed-by: Frank Li > --- > drivers/pci/controller/dwc/pci-imx6.c | 41 ++++++++++++++------------- > 1 file changed, 22 insertions(+), 19 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 06d22f23c6b3..d70e6c427976 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -236,11 +236,11 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie) > > id = imx_pcie->controller_id; > > - /* If mode_mask is 0, then generic PHY driver is used to set the mode */ > + /* If mode_mask is 0, generic PHY driver is used to set the mode */ > if (!drvdata->mode_mask[0]) > return; > > - /* If mode_mask[id] is zero, means each controller have its individual gpr */ > + /* If mode_mask[id] is 0, each controller has its individual GPR */ > if (!drvdata->mode_mask[id]) > id = 0; > > @@ -377,14 +377,15 @@ static int pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 data) > > static int imx8mq_pcie_init_phy(struct imx_pcie *imx_pcie) > { > - /* TODO: Currently this code assumes external oscillator is being used */ > + /* TODO: This code assumes external oscillator is being used */ > regmap_update_bits(imx_pcie->iomuxc_gpr, > imx_pcie_grp_offset(imx_pcie), > IMX8MQ_GPR_PCIE_REF_USE_PAD, > IMX8MQ_GPR_PCIE_REF_USE_PAD); > /* > - * Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is > - * supplied by 3.3V, the VREG_BYPASS should be cleared to zero. > + * Per the datasheet, the PCIE_VPH is suggested to be 1.8V. If the > + * PCIE_VPH is supplied by 3.3V, the VREG_BYPASS should be cleared > + * to zero. > */ > if (imx_pcie->vph && regulator_get_voltage(imx_pcie->vph) > 3000000) > regmap_update_bits(imx_pcie->iomuxc_gpr, > @@ -571,7 +572,7 @@ static int imx_pcie_attach_pd(struct device *dev) > DL_FLAG_PM_RUNTIME | > DL_FLAG_RPM_ACTIVE); > if (!link) { > - dev_err(dev, "Failed to add device_link to pcie pd.\n"); > + dev_err(dev, "Failed to add device_link to pcie pd\n"); > return -EINVAL; > } > > @@ -584,7 +585,7 @@ static int imx_pcie_attach_pd(struct device *dev) > DL_FLAG_PM_RUNTIME | > DL_FLAG_RPM_ACTIVE); > if (!link) { > - dev_err(dev, "Failed to add device_link to pcie_phy pd.\n"); > + dev_err(dev, "Failed to add device_link to pcie_phy pd\n"); > return -EINVAL; > } > > @@ -605,10 +606,10 @@ static int imx6q_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) > /* power up core phy and enable ref clock */ > regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); > /* > - * the async reset input need ref clock to sync internally, > + * The async reset input need ref clock to sync internally, > * when the ref clock comes after reset, internal synced > * reset time is too short, cannot meet the requirement. > - * add one ~10us delay here. > + * Add a ~10us delay here. > */ > usleep_range(10, 100); > regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); > @@ -880,6 +881,7 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > > if (imx_pcie->drvdata->flags & > IMX_PCIE_FLAG_IMX_SPEED_CHANGE) { > + > /* > * On i.MX7, DIRECT_SPEED_CHANGE behaves differently > * from i.MX6 family when no link speed transition > @@ -888,7 +890,6 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > * which will cause the following code to report false > * failure. > */ > - > ret = imx_pcie_wait_for_speed_change(imx_pcie); > if (ret) { > dev_err(dev, "Failed to bring link up!\n"); > @@ -1091,15 +1092,16 @@ static const struct pci_epc_features imx8q_pcie_epc_features = { > }; > > /* > - * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme > - * ================================================================================================ > - * BAR0 | Enable | 64-bit | 1 MB | Programmable Size > - * BAR1 | Disable | 32-bit | 64 KB | Fixed Size > - * BAR1 should be disabled if BAR0 is 64bit. > - * BAR2 | Enable | 32-bit | 1 MB | Programmable Size > - * BAR3 | Enable | 32-bit | 64 KB | Programmable Size > - * BAR4 | Enable | 32-bit | 1M | Programmable Size > - * BAR5 | Enable | 32-bit | 64 KB | Programmable Size > + * | Default | Default | Default | BAR Sizing > + * BAR# | Enable? | Type | Size | Scheme > + * ======================================================= > + * BAR0 | Enable | 64-bit | 1 MB | Programmable Size > + * BAR1 | Disable | 32-bit | 64 KB | Fixed Size > + * (BAR1 should be disabled if BAR0 is 64-bit) > + * BAR2 | Enable | 32-bit | 1 MB | Programmable Size > + * BAR3 | Enable | 32-bit | 64 KB | Programmable Size > + * BAR4 | Enable | 32-bit | 1 MB | Programmable Size > + * BAR5 | Enable | 32-bit | 64 KB | Programmable Size > */ > static const struct pci_epc_features imx95_pcie_epc_features = { > .msi_capable = true, > @@ -1260,6 +1262,7 @@ static int imx_pcie_resume_noirq(struct device *dev) > ret = imx_pcie_deassert_core_reset(imx_pcie); > if (ret) > return ret; > + > /* > * Using PCIE_TEST_PD seems to disable MSI and powers down the > * root complex. This is why we have to setup the rc again and > -- > 2.34.1 >