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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6e43babcc32sm8154696d6.113.2025.02.06.10.33.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2025 10:33:57 -0800 (PST) Date: Thu, 6 Feb 2025 13:33:55 -0500 From: Gregory Price To: Terry Bowman Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, nifan.cxl@gmail.com, dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, dan.j.williams@intel.com, bhelgaas@google.com, mahesh@linux.ibm.com, ira.weiny@intel.com, oohall@gmail.com, Benjamin.Cheatham@amd.com, rrichter@amd.com, nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com, lukas@wunner.de, ming.li@zohomail.com, PradeepVineshReddy.Kodamati@amd.com, alucerop@amd.com Subject: Re: [PATCH v5 05/16] PCI/AER: Add CXL PCIe Port correctable error support in AER service driver Message-ID: References: <20250107143852.3692571-1-terry.bowman@amd.com> <20250107143852.3692571-6-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250107143852.3692571-6-terry.bowman@amd.com> On Tue, Jan 07, 2025 at 08:38:41AM -0600, Terry Bowman wrote: > The AER service driver supports handling Downstream Port Protocol Errors in > Restricted CXL host (RCH) mode also known as CXL1.1. It needs the same > functionality for CXL PCIe Ports operating in Virtual Hierarchy (VH) > mode.[1] > > CXL and PCIe Protocol Error handling have different requirements that > necessitate a separate handling path. The AER service driver may try to > recover PCIe uncorrectable non-fatal errors (UCE). The same recovery is not > suitable for CXL PCIe Port devices because of potential for system memory > corruption. Instead, CXL Protocol Error handling must use a kernel panic > in the case of a fatal or non-fatal UCE. The AER driver's PCIe Protocol > Error handling does not panic the kernel in response to a UCE. > Naive question: is a panic actually required if the memory is a userland resource? The code in arch/x86/kernel/cpu/mce/core.c suggests we may not panic if an uncorrectable error occurs in this fashion, but simply a SIGBUS. Unless this is down the wrong pipe - in which case disregard. I'm still digging through background on this patch set so I may be barking up the wrong tree. ~Gregory