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Mon, 10 Mar 2025 17:23:34 +0000 Date: Mon, 10 Mar 2025 13:23:29 -0400 From: Rodrigo Vivi To: Anshuman Gupta CC: , , , , , , , , , Subject: Re: [RFC 3/6] drm/xe/vrsr: Apis to init and enable VRSR feature Message-ID: References: <20250224164849.3746751-1-anshuman.gupta@intel.com> <20250224164849.3746751-4-anshuman.gupta@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250224164849.3746751-4-anshuman.gupta@intel.com> X-ClientProxiedBy: MW4PR03CA0110.namprd03.prod.outlook.com (2603:10b6:303:b7::25) To SA1PR11MB8427.namprd11.prod.outlook.com (2603:10b6:806:373::19) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA1PR11MB8427:EE_|SA1PR11MB7061:EE_ X-MS-Office365-Filtering-Correlation-Id: 56850fc5-b198-4d2c-f1db-08dd5ff848d8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?qeDVNYr2kQvQhuPc7Hscvm99XJK8JOgSZahmMS9BnHEoS/cqpClwmkG5EPNf?= =?us-ascii?Q?6jfTdxVVplNobIgMkAH4u7pS2kTzNo7xzrzqmhxrGz8/7BvjY4TVxU/SxZwR?= =?us-ascii?Q?DJjCMztokQuRJgG7TTVbSlxLRbYUXtAAlXz0DklGW45KMW0WG1z4Qokl7Gln?= =?us-ascii?Q?CM7UjdFfC/YuTGeQ3l8qu1H+RHfeRip4xGr1VKem+28LbSnbPGBmKwB0pIBz?= =?us-ascii?Q?OZct8eGCnUqdnNSEoMBaEniKZsX06HVaqNC/KJ69HUBkt0Z0DI1N+6Tdzufp?= =?us-ascii?Q?CUVRqQ96ri/5prbCtg2RkxhIqSv3tZ5MNdY7I/Gnur+M4+tqY8vM+AbH6/b4?= =?us-ascii?Q?5W/eYj11E+wt2u3JZdIX54YNHQzskQqjzIGhfyPhFpcDEW3DeFL0bNPsL7iF?= =?us-ascii?Q?A8NFFWM/fP1vSMK/5EiyHdryFX1dAKvMi1Xyc7RTtJqkB88iVhneL3YfDf9P?= =?us-ascii?Q?NhIzhl1/NbBAfXXDXNXzfL2v/p6pakGfEv/4YTSM2eAF/CvcuzdPWId6FRQ9?= =?us-ascii?Q?ca6fmWU0ktzG7nOjtRmus3g/JZI6lq/XFHYUUlux0QsIbAY9hkVIweAjMdzo?= =?us-ascii?Q?kWvkqNzj2yleI5XLUVgg1FNs1ylg7Q5K9pak+/FNcsWsyO6XhIzEu/Xco5Jo?= =?us-ascii?Q?7j9iRy8KUq47VS/3lGNYVlvoLInTc4y0cgxTf6Q2LnBu/y/pGgzapJ8tln51?= =?us-ascii?Q?wv06rYa+jLqMP7qXxLxMF3Ckb3gZ3lJhRpqva2ElgAnRZVYC4MERF52Dg5iU?= =?us-ascii?Q?xEpqkulYGjgm/vGA9M8NonHfuaZaVLoPSBjQmPPyfUzo4PTzsCzsZDWy7WIA?= =?us-ascii?Q?lylGh7HywMI11JEd1EIE2YA9GiGP/ejzPN66FUmpSoGosBfDqI4k9giyuOz1?= =?us-ascii?Q?BeP62I3ROITpTjwxk/XBVXnw31/24IkgOuMpFRbbzN+BN3FmyD3HVDdxgRWX?= =?us-ascii?Q?uwaOeL97lSxKaEY5pEb2y1JN51I1/HgClH2lUiVW8O22+McYuWLbA4A9Bl0h?= =?us-ascii?Q?R7QcQZyM79lAMdO/6KsI6PIHm6Aby50k5josOSGl8lxaEpgsyLsVcAS+1QNE?= =?us-ascii?Q?RN58GihXwoEWsCzOAYF/r9oX8aOm8nv8Ag8R907FI1PYZvxAK/vC1LOiJq3d?= =?us-ascii?Q?S5ggvA7IAk7nMOjQsInyffCavKQ0PR0e5hhcIUgbVSp2BOx3622NWfeK6c5e?= =?us-ascii?Q?tsugiKabCdcya4qUK464yePauVbfDdIoU4BqEe4cMfuSWbZP+wOUrI3xi2Er?= =?us-ascii?Q?4dsqlM5+IgH8+07oE3Uh2ciJ7e0QMSkTAYhLpqWoRHn8D6eJtbYQvAWen6p0?= =?us-ascii?Q?Z1z/WpGDKHIkwgU/yzgiAgTJV6O/d+Bw0gtCb5qlQArTx6lHiXcOHrGmxTcm?= =?us-ascii?Q?G/qGVVxUWHkFPuNBFIEftYnEcJrhS3X0c3VGNmc7TdZ1fUIt83hzFdgjaIyq?= =?us-ascii?Q?/sojf2yGgLtqDmQzZyRh5ByY4uXQ/BpSDiKVh9wejj7a/uaJiFLwZtUO/6N1?= =?us-ascii?Q?zdr3WbSIPr8cX6HM+ZkyInxClmd7vxbb8jSLUj7MNTe5Ts9y6BqedBraQ2wZ?= =?us-ascii?Q?bmCZcfbP8AWztON9eocrjZ5ZUSQxn0GyEmFOZ2/hDMd6eZERyfyvGKtWx+qL?= =?us-ascii?Q?uw=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 56850fc5-b198-4d2c-f1db-08dd5ff848d8 X-MS-Exchange-CrossTenant-AuthSource: SA1PR11MB8427.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Mar 2025 17:23:33.9005 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wmwJ1ygIdhhGUdB4zceC9asn03Ze6kfIMI866fkIWBePvv9kOr3S4Q89o6g/nKAzwVDZ/C2pptGKfnzQ9PT/QA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR11MB7061 X-OriginatorOrg: intel.com On Mon, Feb 24, 2025 at 10:18:46PM +0530, Anshuman Gupta wrote: > From: Badal Nilawar > > APIs to enable and initialize VRSR feature. > > Signed-off-by: Badal Nilawar > Signed-off-by: Anshuman Gupta > --- > drivers/gpu/drm/xe/xe_device_types.h | 1 + > drivers/gpu/drm/xe/xe_pcode_api.h | 8 +++ > drivers/gpu/drm/xe/xe_pm.c | 91 ++++++++++++++++++++++++++++ > drivers/gpu/drm/xe/xe_pm.h | 3 + > 4 files changed, 103 insertions(+) > > diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h > index c2ab2c91c968..da7946b75cd5 100644 > --- a/drivers/gpu/drm/xe/xe_device_types.h > +++ b/drivers/gpu/drm/xe/xe_device_types.h > @@ -7,6 +7,7 @@ > #define _XE_DEVICE_TYPES_H_ > > #include > +#include > > #include > #include > diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h > index 2bae9afdbd35..17a90b2c6737 100644 > --- a/drivers/gpu/drm/xe/xe_pcode_api.h > +++ b/drivers/gpu/drm/xe/xe_pcode_api.h > @@ -42,6 +42,14 @@ > #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */ > #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0) > > +#define PCODE_D3_VRAM_SELF_REFRESH 0x71 > +#define PCODE_D3_VRSR_SC_DISABLE 0x0 > +#define PCODE_D3_VRSR_SC_ENABLE 0x1 > +#define PCODE_D3_VRSR_SC_AUX_PL_AND_PERST_DELAY 0x2 > +#define PCODE_D3_VRSR_PERST_SHIFT 16 > +#define POWER_D3_VRSR_PSERST_MASK REG_GENMASK(31, 16) > +#define POWER_D3_VRSR_AUX_PL_MASK REG_GENMASK(15, 0) > + > #define PCODE_FREQUENCY_CONFIG 0x6e > /* Frequency Config Sub Commands (param1) */ > #define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0 > diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c > index dead236355d8..32583651988f 100644 > --- a/drivers/gpu/drm/xe/xe_pm.c > +++ b/drivers/gpu/drm/xe/xe_pm.c > @@ -23,6 +23,7 @@ > #include "xe_guc.h" > #include "xe_irq.h" > #include "xe_mmio.h" > +#include "xe_pcode_api.h" > #include "xe_pcode.h" > #include "xe_pxp.h" > #include "regs/xe_regs.h" > @@ -85,6 +86,92 @@ static struct lockdep_map xe_pm_runtime_nod3cold_map = { > }; > #endif > > +/** > + * xe_pm_init_vrsr - Initialize VRAM self refresh > + * @xe: The xe device > + * > + * This function reads the AUX power and PERST assertion delay from pcode. > + * Then request host BIOS via ACPI _DSM to grant required AUX power and PERST > + * assertion delay. > + * > + * Return: returns 0 on success and errno on failure > + */ > +int why not void? we are not checking it anyway... > xe_pm_init_vrsr(struct xe_device *xe) perhaps xe_pm_d3cold_vrsr_init() > +{ > + struct xe_tile *root_tile = xe_device_get_root_tile(xe); > + struct pci_dev *pdev = to_pci_dev(xe->drm.dev); > + struct pci_dev *root_pdev; > + int ret; > + u32 uval; > + u32 aux_pwr_limit; > + u32 perst_delay; > + > + root_pdev = pcie_find_root_port(pdev); > + if (!root_pdev) > + return -EINVAL; > + > + /* Avoid Illegal Subcommand error */ > + if (xe->info.platform != XE_BATTLEMAGE) > + return -ENXIO; I wonder if we should do a has_d3cold_vrsr flag for this, or at least move this check earlier. > + > + ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_D3_VRAM_SELF_REFRESH, > + PCODE_D3_VRSR_SC_AUX_PL_AND_PERST_DELAY, 0), > + &uval, NULL); > + > + if (ret) > + return ret; > + > + aux_pwr_limit = REG_FIELD_GET(POWER_D3_VRSR_AUX_PL_MASK, uval); > + perst_delay = REG_FIELD_GET(POWER_D3_VRSR_PSERST_MASK, uval); > + > + drm_dbg(&xe->drm, "AUX POWER LIMIT =%d\n", aux_pwr_limit); > + drm_dbg(&xe->drm, "PERST Assertion delay =%d\n", perst_delay); > + > + ret = pci_acpi_request_d3cold_aux_power(root_pdev, aux_pwr_limit); > + if (ret) > + goto vrsr; > + > + ret = pci_acpi_add_perst_assertion_delay(root_pdev, perst_delay); > + if (ret) > + goto vrsr; > + > + return ret; > + > +vrsr: > + drm_err(&xe->drm, "ACPI DSM failed, VRSR is not capable\n"); > + xe->d3cold.vrsr_capable = false; > + return ret; > +} > + > +/** > + * xe_pm_enable_vrsr - Enable VRAM self refresh > + * @xe: The xe device. > + * @enable: true: Enable, false: Disable > + * > + * This function enables the VRSR feature in D3Cold path. > + * > + * Return: It returns 0 on success and errno on failure. > + */ > +int xe_pm_enable_vrsr(struct xe_device *xe, bool enable) > +{ > + struct xe_tile *root_tile = xe_device_get_root_tile(xe); > + int ret; > + u32 uval = 0; > + > + /* Avoid Illegal Subcommand error */ > + if (xe->info.platform != XE_BATTLEMAGE) > + return -ENXIO; > + > + if (enable) > + ret = xe_pcode_write(root_tile, PCODE_MBOX(PCODE_D3_VRAM_SELF_REFRESH, > + PCODE_D3_VRSR_SC_ENABLE, 0), uval); > + else > + ret = xe_pcode_write(root_tile, PCODE_MBOX(PCODE_D3_VRAM_SELF_REFRESH, > + PCODE_D3_VRSR_SC_DISABLE, 0), uval); > + > + return ret; > +} > + > /** > * xe_rpm_reclaim_safe() - Whether runtime resume can be done from reclaim context > * @xe: The xe device. > @@ -330,6 +417,10 @@ int xe_pm_init(struct xe_device *xe) > return err; > > xe->d3cold.vrsr_capable = xe_pm_vrsr_capable(xe); > + if (xe->d3cold.vrsr_capable) { > + drm_dbg(&xe->drm, "vram sr capable\n"); > + xe_pm_init_vrsr(xe); > + } perhaps move this piece of code entirely to the init function itself? > } > > xe_pm_runtime_init(xe); > diff --git a/drivers/gpu/drm/xe/xe_pm.h b/drivers/gpu/drm/xe/xe_pm.h > index 998d1ed64556..c9f176912b46 100644 > --- a/drivers/gpu/drm/xe/xe_pm.h > +++ b/drivers/gpu/drm/xe/xe_pm.h > @@ -35,4 +35,7 @@ bool xe_rpm_reclaim_safe(const struct xe_device *xe); > struct task_struct *xe_pm_read_callback_task(struct xe_device *xe); > int xe_pm_module_init(void); > > +int xe_pm_init_vrsr(struct xe_device *xe); > +int xe_pm_enable_vrsr(struct xe_device *xe, bool enable); > + > #endif > -- > 2.34.1 >