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Fri, 7 Mar 2025 21:50:07 +0000 Date: Fri, 7 Mar 2025 16:50:02 -0500 From: Rodrigo Vivi To: Anshuman Gupta CC: , , , , , , , , , Subject: Re: [RFC 2/6] drm/xe/vrsr: Detect vrsr capability Message-ID: References: <20250224164849.3746751-1-anshuman.gupta@intel.com> <20250224164849.3746751-3-anshuman.gupta@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250224164849.3746751-3-anshuman.gupta@intel.com> X-ClientProxiedBy: MW4PR02CA0028.namprd02.prod.outlook.com (2603:10b6:303:16d::7) To CYYPR11MB8430.namprd11.prod.outlook.com (2603:10b6:930:c6::19) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CYYPR11MB8430:EE_|PH7PR11MB6748:EE_ X-MS-Office365-Filtering-Correlation-Id: c7202241-f4d2-4839-edc0-08dd5dc20667 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?M1+6ymfatvzBcC7CqjCy1n6WjoVYin8PpsYoxrnkBpHUaWO9turiOLWnQipS?= =?us-ascii?Q?VU8Lo+n4pNdB5NuJ81pvg4tU3Urp8+Rs9j9cNcHIk+BM+7lhpNmJojdoIUpw?= =?us-ascii?Q?oSn6eIDyqxvc0NHuHhnZumOji08yvYy0MZCAJtOeQ6N2QV76bULBrvxgbL8n?= =?us-ascii?Q?Egk1I+eROZcuNOJ1osboGo4oLkIUqAJWDc9T3J2ud3+S/LoUC1svT1QjmZPq?= =?us-ascii?Q?y9jw94EP4YvAkDs8X+Wfod5WnknQqP+4RpBdks3IAGMC0NZJzIa6Vwt1oY/D?= =?us-ascii?Q?8ECmGKcL8B9jfCCxBUuWdXcIryc9oFpszp5MfXmQxH98q4i+VWy0IE7Fghzb?= =?us-ascii?Q?E5eWNd+BnKmg143bZmLZAP19No9wkcQNZ8m0jjVmyqzleTXSUj98QhY2hkA1?= =?us-ascii?Q?PCHvYJupXBQEyGoJfnBrZqGNg866JBZ0Bt/SgwjMo6Z1AUftl4D2VJe/I6WK?= =?us-ascii?Q?gjGiQ+9OgZ6uJmRmz3XRe6KaS61czbVE6M9N89EL6sDaECzG9kyAr+uIsUl/?= =?us-ascii?Q?AU3ncZJxvw+72H1n5vuA4nYRSMsvH1Wz+K8KYc/qUA9ZHOCwZFr2rtuhgOrX?= =?us-ascii?Q?wprwt1TAc+zLpeb91WMW6LemEI6/x/QQCJ3g4yZ1Z99hfzZbuq1W7yG+m+db?= =?us-ascii?Q?5H75f9CtBdWMeNpqM7emCrlw5Q47bjZNMk7GyZI+N/xdToAhxOqrVdscBKYk?= =?us-ascii?Q?Sd4ZFrGGBVABxDTCuD0MY6ww+eBE6+JX7q1MQ0dJc/X8m6Q1tfOuUiTnwgh/?= =?us-ascii?Q?JEQI27eEcBemxLmk6BIrRx7Jnhd5W2hrMn0E/uUqEiSQlGdFyBCPmC/plapx?= =?us-ascii?Q?qUj4Y7DGxvUiScDPIYfgrNNosCymI7Hz1EgAP5TbGNUPsVhdGZtAKa1sYfoB?= =?us-ascii?Q?FKyy4rVMhmysyORqCKPYCcxmq7fjB/PIyvv4z9OyOLyO1VAWJIQtQHo2ALm2?= =?us-ascii?Q?AfpSn0lpbq+fPJsIAmvVwnmVC97pwF8ir9M8jvSH43eAvnlCpS9Q3sqEmROJ?= =?us-ascii?Q?laRkAqjd9l7llBYuwO5eEupTUyrvpyglDLbxw0Rq3wutk3nENNiboCmrSuCF?= =?us-ascii?Q?vnLHPIVCQKodUK0nVtA6jDj1zjl8KKz4DKRRFm8CP+YHHvXQoIGaDiRiT+fw?= =?us-ascii?Q?Z7wIO75ViB4KMEvNpgdVxyvQ8BZPGNo4iEcV8UMGfd2wg+UrwfQ6vJ/hByVU?= =?us-ascii?Q?WUjkKbGA1ErgOkPhPN0hzO/sfxq6jyARdjC76PcGgGU9D/9udKjzueG7MjzG?= =?us-ascii?Q?bTqyuw9dZpjC65ZRewQk25GL/H++RIpgIOFdUOyk3xQ6tohRprCS3rZjoi9B?= =?us-ascii?Q?QLd9E8R2yrTKn2+Oirb0yBRzqasgn+mQLGKDRBWN22RSy41lxNR8blZDHY+r?= =?us-ascii?Q?AGqMSWwyWl/ZEscxTEQEer3FyVdEB7AH5lXL+ShfS4REebx5m7eDMrhoth8f?= =?us-ascii?Q?Wr0gFEWgN9Stj4kiYFNGTt8hEQZc+3I4fH2lEY8OCcMqCeWGSQXWBGf6riNx?= =?us-ascii?Q?8nTHVl9aa3NApXBxi3T1K0FtwU4FtNbAiALDxDCq77KZ0vlak/sdkfx5fDub?= =?us-ascii?Q?2zFXmizgvF0JS5qhYJtvr6MOeoggOYYfk42opLm2VHMQ5wtgG9eHGLlf8gCc?= =?us-ascii?Q?xA=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: c7202241-f4d2-4839-edc0-08dd5dc20667 X-MS-Exchange-CrossTenant-AuthSource: CYYPR11MB8430.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Mar 2025 21:50:07.1398 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: vinlN1o49YKNEDo7IFiSb6C1wqR2PSFflH1mW588mrB/fkN44v6khqVwazH/GgXBGf1pUmfymHVQgXMhvCOwxA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR11MB6748 X-OriginatorOrg: intel.com On Mon, Feb 24, 2025 at 10:18:45PM +0530, Anshuman Gupta wrote: > Detect VRAM Self Refresh(vrsr) Capability. > > Signed-off-by: Anshuman Gupta > --- > drivers/gpu/drm/xe/regs/xe_regs.h | 3 +++ > drivers/gpu/drm/xe/xe_device_types.h | 4 ++++ > drivers/gpu/drm/xe/xe_pm.c | 27 +++++++++++++++++++++++++++ > 3 files changed, 34 insertions(+) > > diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h > index 6cf282618836..21563e9d958b 100644 > --- a/drivers/gpu/drm/xe/regs/xe_regs.h > +++ b/drivers/gpu/drm/xe/regs/xe_regs.h > @@ -57,6 +57,9 @@ > #define MTL_MPE_FREQUENCY XE_REG(0x13802c) > #define MTL_RPE_MASK REG_GENMASK(8, 0) > > +#define VRAM_CAPABILITY XE_REG(0x138144) > +#define VRAM_SUPPORTED REG_BIT(0) I'm missing a 'SR' mention here. I know the register name is VRAM_CAPABILITY what looks horrible, but let's live with it, but we could then use same or similar terminology from BSPec: VRAM_SR_CAP or VRAM_SR_CAP_SUPPORTED or VRAM_SR_SUPPORTED at least? with some mention to SR here: Reviewed-by: Rodrigo Vivi > + > #define VF_CAP_REG XE_REG(0x1901f8, XE_REG_OPTION_VF) > #define VF_CAP REG_BIT(0) > > diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h > index 4656305dd45a..c2ab2c91c968 100644 > --- a/drivers/gpu/drm/xe/xe_device_types.h > +++ b/drivers/gpu/drm/xe/xe_device_types.h > @@ -490,6 +490,9 @@ struct xe_device { > /** @d3cold.allowed: Indicates if d3cold is a valid device state */ > bool allowed; > > + /** @d3cold.vrsr_capable: Indicates if d3cold VRAM Self Refresh is supported */ > + bool vrsr_capable; > + > /** > * @d3cold.vram_threshold: > * > @@ -500,6 +503,7 @@ struct xe_device { > * Default threshold value is 300mb. > */ > u32 vram_threshold; > + > /** @d3cold.lock: protect vram_threshold */ > struct mutex lock; > } d3cold; > diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c > index 12200be7b43d..dead236355d8 100644 > --- a/drivers/gpu/drm/xe/xe_pm.c > +++ b/drivers/gpu/drm/xe/xe_pm.c > @@ -17,12 +17,15 @@ > #include "xe_bo_evict.h" > #include "xe_device.h" > #include "xe_device_sysfs.h" > +#include "xe_force_wake.h" > #include "xe_ggtt.h" > #include "xe_gt.h" > #include "xe_guc.h" > #include "xe_irq.h" > +#include "xe_mmio.h" > #include "xe_pcode.h" > #include "xe_pxp.h" > +#include "regs/xe_regs.h" > #include "xe_trace.h" > #include "xe_wa.h" > > @@ -236,6 +239,28 @@ static bool xe_pm_pci_d3cold_capable(struct xe_device *xe) > return true; > } > > +static bool xe_pm_vrsr_capable(struct xe_device *xe) > +{ > + struct xe_mmio *mmio = xe_root_tile_mmio(xe); > + unsigned int fw_ref; > + struct xe_gt *gt; > + u32 val; > + > + gt = xe_root_mmio_gt(xe); > + > + if (!xe->info.probe_display) > + return false; > + > + fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); > + if (!fw_ref) > + return false; > + > + val = xe_mmio_read32(mmio, VRAM_CAPABILITY); > + xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); > + > + return val & VRAM_SUPPORTED; > +} > + > static void xe_pm_runtime_init(struct xe_device *xe) > { > struct device *dev = xe->drm.dev; > @@ -303,6 +328,8 @@ int xe_pm_init(struct xe_device *xe) > err = xe_pm_set_vram_threshold(xe, DEFAULT_VRAM_THRESHOLD); > if (err) > return err; > + > + xe->d3cold.vrsr_capable = xe_pm_vrsr_capable(xe); > } > > xe_pm_runtime_init(xe); > -- > 2.34.1 >