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Wed, 12 Mar 2025 09:39:44 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52C9dgkR020391 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Mar 2025 09:39:43 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 12 Mar 2025 02:39:38 -0700 Date: Wed, 12 Mar 2025 15:09:34 +0530 From: Varadarajan Narayanan To: Krzysztof Kozlowski CC: , , , , , , , , , , , , , , Subject: Re: [PATCH v12 1/4] dt-bindings: PCI: qcom: Add MHI registers for IPQ9574 Message-ID: References: <20250312084330.873994-1-quic_varada@quicinc.com> <20250312084330.873994-2-quic_varada@quicinc.com> <7b2d7f14-4274-4ff0-87a6-ac3dd649df4e@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <7b2d7f14-4274-4ff0-87a6-ac3dd649df4e@kernel.org> X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: VLZnR-Gwgi09wzAZYhOChL3XibPlTXpM X-Proofpoint-GUID: VLZnR-Gwgi09wzAZYhOChL3XibPlTXpM X-Authority-Analysis: v=2.4 cv=TIhFS0la c=1 sm=1 tr=0 ts=67d15660 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=kj9zAlcOel0A:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=FAg4eJUAi5izC7YpO0UA:9 a=CjuIK1q_8ugA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-12_03,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 mlxlogscore=970 mlxscore=0 clxscore=1015 bulkscore=0 malwarescore=0 suspectscore=0 spamscore=0 phishscore=0 impostorscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503120065 On Wed, Mar 12, 2025 at 09:46:41AM +0100, Krzysztof Kozlowski wrote: > On 12/03/2025 09:43, Varadarajan Narayanan wrote: > > Append the MHI register range to IPQ9574. > > Why? This is needed for ipq5332 to use ipq9574 as fallback compatible. > > Fixes: e0662dae178d ("dt-bindings: PCI: qcom: Document the IPQ9574 PCIe controller") > > What is being fixed here? Ok, will remove this. > > Signed-off-by: Varadarajan Narayanan > > --- > > New patch introduced in this patchset. MHI range was missed in the > > initial post > > --- > > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > index 8f628939209e..77e66ab8764f 100644 > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > @@ -175,7 +175,7 @@ allOf: > > properties: > > reg: > > minItems: 5 > > - maxItems: 5 > > + maxItems: 6 > > Why qcom,pcie-ipq6018 gets mhi? Nothing in commit msg mentions ipq6018. Didn't mention ipq6018 as I was under the impression that 'minItems: 5' would apply for ipq6018. > > reg-names: > > items: > > - const: dbi # DesignWare PCIe registers > > @@ -183,6 +183,7 @@ allOf: > > - const: atu # ATU address space > > - const: parf # Qualcomm specific registers > > - const: config # PCIe configuration space > > + - const: mhi # MHI registers > > Never tested - you introduce new warnings. AGAIN. > > Properties xxx and xxx-names must have always the same constraints. Ok, will add 'minItems: 5' here. Thanks Varada