From: Robert Richter <rrichter@amd.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
Terry Bowman <terry.bowman@amd.com>, <alison.schofield@intel.com>,
<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
<bwidawsk@kernel.org>, <dan.j.williams@intel.com>,
<dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>,
Oliver O'Halloran <oohall@gmail.com>,
Mahesh J Salgaonkar <mahesh@linux.ibm.com>,
<linuxppc-dev@lists.ozlabs.org>, <linux-pci@vger.kernel.org>
Subject: Re: [PATCH v3 6/6] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
Date: Fri, 14 Apr 2023 13:58:03 +0200 [thread overview]
Message-ID: <ZDk/y/w5IjuRkPyu@rric.localdomain> (raw)
In-Reply-To: <20230413180508.00003f13@Huawei.com>
On 13.04.23 18:05:08, Jonathan Cameron wrote:
> On Thu, 13 Apr 2023 15:38:07 +0200
> Robert Richter <rrichter@amd.com> wrote:
>
> > On 12.04.23 16:29:01, Bjorn Helgaas wrote:
> > > On Tue, Apr 11, 2023 at 01:03:02PM -0500, Terry Bowman wrote:
> > > With the exception of this function, this patch looks like all CXL
> > > code that maybe could be with other CXL code. Would require making
> > > pcie_walk_rcec() available outside drivers/pci, I guess.
> >
> > Even this is CXL code, it implements AER support and fits better here
> > around AER code. Export of pcie_walk_rcec() (and others?) is not the
> > main issue here. CXL drivers can come as modules and would need to
> > register a hook at the aer handler. This would add even more
> > complexity here. In contrast, current solution just adds two functions
> > for enablement and handling which are empty stubs if code is disabled.
> >
> > I could move that code to aer_cxl.c similar to aer_inject.c. Since the
> > CXL part is small compared to the remaining aer code I left it in
> > aer.c. Also, it is guarded by #ifdef which additionally encapsulates
> > it.
> >
>
> To throw another option in there (what Bjorn suggested IIRC for the more
> general case..)
>
> Just enable internal errors always. No need to know if they are CXL
> or something else.
>
> There will/might be fallout and it will be fun.
I left the fun part to others. :-)
If some PCI root port goes crazy it tears down the whole system, would
avoid that.
Since internal error are implementation specific, I would only enable
them once a handler exists. What's why enablement is limited to CXL
RCECs only.
-Robert
next prev parent reply other threads:[~2023-04-14 11:58 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20230411180302.2678736-1-terry.bowman@amd.com>
2023-04-11 18:02 ` [PATCH v3 3/6] PCI/AER: Export cper_print_aer() for use by modules Terry Bowman
2023-04-13 16:13 ` Jonathan Cameron
2023-04-17 23:11 ` Dan Williams
2023-04-11 18:03 ` [PATCH v3 5/6] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-04-12 22:02 ` Bjorn Helgaas
2023-04-13 11:40 ` Robert Richter
2023-04-14 21:32 ` Bjorn Helgaas
2023-04-17 22:00 ` Robert Richter
2023-04-19 14:17 ` Robert Richter
2023-04-14 12:19 ` Jonathan Cameron
2023-04-14 14:35 ` Robert Richter
2023-04-17 16:54 ` Jonathan Cameron
2023-04-17 20:36 ` Robert Richter
2023-04-18 1:01 ` Dan Williams
2023-04-19 13:30 ` Robert Richter
2023-04-11 18:03 ` [PATCH v3 6/6] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-04-12 21:29 ` Bjorn Helgaas
2023-04-13 13:38 ` Robert Richter
2023-04-13 17:05 ` Jonathan Cameron
2023-04-14 11:58 ` Robert Richter [this message]
2023-04-14 21:49 ` Bjorn Helgaas
2023-04-13 17:01 ` Jonathan Cameron
2023-04-13 22:52 ` Ira Weiny
2023-04-14 11:21 ` Robert Richter
2023-04-14 11:55 ` Jonathan Cameron
2023-04-14 14:47 ` Robert Richter
2023-04-18 2:37 ` Dan Williams
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