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[34.82.65.13]) by smtp.gmail.com with ESMTPSA id p11-20020a170902a40b00b001a240f053aasm918792plq.180.2023.04.19.12.29.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 12:29:17 -0700 (PDT) Date: Wed, 19 Apr 2023 12:29:14 -0700 From: William McVicker To: Ajay Agarwal Cc: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Nikhil Devshatwar , Manu Gautam , Bjorn Helgaas , Sajid Dalvi , linux-pci@vger.kernel.org Subject: Re: [PATCH v4] PCI: dwc: Wait for link up only if link is started Message-ID: References: <20230412093425.3659088-1-ajayagarwal@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230412093425.3659088-1-ajayagarwal@google.com> X-ccpol: medium Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 04/12/2023, Ajay Agarwal wrote: > In dw_pcie_host_init() regardless of whether the link has been > started or not, the code waits for the link to come up. Even in > cases where start_link() is not defined the code ends up spinning > in a loop for 1 second. Since in some systems dw_pcie_host_init() > gets called during probe, this one second loop for each pcie > interface instance ends up extending the boot time. > > Wait for the link up in only if the start_link() is defined. > > Signed-off-by: Sajid Dalvi > Signed-off-by: Ajay Agarwal > --- > Changelog since v3: > - Run dw_pcie_start_link() only if link is not already up > > Changelog since v2: > - Wait for the link up if start_link() is really defined. > - Print the link status if the link is up on init. > > .../pci/controller/dwc/pcie-designware-host.c | 13 ++++++++---- > drivers/pci/controller/dwc/pcie-designware.c | 20 ++++++++++++------- > drivers/pci/controller/dwc/pcie-designware.h | 1 + > 3 files changed, 23 insertions(+), 11 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 9952057c8819..cf61733bf78d 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -485,14 +485,19 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > if (ret) > goto err_remove_edma; > > - if (!dw_pcie_link_up(pci)) { > + if (dw_pcie_link_up(pci)) { > + dw_pcie_print_link_status(pci); > + } else { > ret = dw_pcie_start_link(pci); > if (ret) > goto err_remove_edma; > - } > > - /* Ignore errors, the link may come up later */ > - dw_pcie_wait_for_link(pci); > + if (pci->ops && pci->ops->start_link) { > + ret = dw_pcie_wait_for_link(pci); > + if (ret) > + goto err_stop_link; > + } > + } > > bridge->sysdata = pp; > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 53a16b8b6ac2..03748a8dffd3 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -644,9 +644,20 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index) > dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0); > } > > -int dw_pcie_wait_for_link(struct dw_pcie *pci) > +void dw_pcie_print_link_status(struct dw_pcie *pci) > { > u32 offset, val; > + > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); > + > + dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", > + FIELD_GET(PCI_EXP_LNKSTA_CLS, val), > + FIELD_GET(PCI_EXP_LNKSTA_NLW, val)); > +} > + > +int dw_pcie_wait_for_link(struct dw_pcie *pci) > +{ > int retries; > > /* Check if the link is up or not */ > @@ -662,12 +673,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) > return -ETIMEDOUT; > } > > - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > - val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); > - > - dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", > - FIELD_GET(PCI_EXP_LNKSTA_CLS, val), > - FIELD_GET(PCI_EXP_LNKSTA_NLW, val)); > + dw_pcie_print_link_status(pci); > > return 0; > } > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 79713ce075cc..615660640801 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -429,6 +429,7 @@ void dw_pcie_setup(struct dw_pcie *pci); > void dw_pcie_iatu_detect(struct dw_pcie *pci); > int dw_pcie_edma_detect(struct dw_pcie *pci); > void dw_pcie_edma_remove(struct dw_pcie *pci); > +void dw_pcie_print_link_status(struct dw_pcie *pci); > > static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) > { > -- > 2.40.0.577.gac1e443424-goog > Thanks for sending this patch Ajay! I tested this on my Pixel 6 with 6.3-rc1. I verified the PCIe RC probes without the 1s delay in dw_pcie_wait_for_link(). Feel free to include Tested-by: Will McVicker