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[34.143.183.41]) by smtp.gmail.com with ESMTPSA id i5-20020a1709026ac500b001b80b342f61sm77877plt.268.2023.07.10.09.21.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 09:21:31 -0700 (PDT) Date: Mon, 10 Jul 2023 21:51:22 +0530 From: Ajay Agarwal To: Johan Hovold , Manivannan Sadhasivam Cc: Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson , Sajid Dalvi Subject: Re: [PATCH] Revert "PCI: dwc: Wait for link up only if link is started" Message-ID: References: <20230706082610.26584-1-johan+linaro@kernel.org> <20230706125811.GD4808@thinkpad> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Fri, Jul 07, 2023 at 02:47:56PM +0200, Johan Hovold wrote: > On Thu, Jul 06, 2023 at 06:28:11PM +0530, Manivannan Sadhasivam wrote: > > On Thu, Jul 06, 2023 at 10:26:10AM +0200, Johan Hovold wrote: > > > > Finally, note that the intel-gw driver is the only driver currently not > > > providing a start_link callback and instead starts the link in its > > > host_init callback, and which may avoid an additional one-second timeout > > > during probe by making the link-up wait conditional. If anyone cares, > > > that can be done in a follow-up patch with a proper motivation. > > > The offending commit is bogus since it makes the intel-gw _special_ w.r.t > > waiting for the link up. Most of the drivers call dw_pcie_host_init() during the > > probe time and they all have to wait for 1 sec if the slot is empty. Mani, can you please explain how my commit made the intel-gw driver special? The intel driver actually fails the dw_pcie_host_init if the link does not come up. That was my motivation behind adding the fail logic in the core driver as well. > > Just to clarify, the intel-gw driver starts the link and waits for link > up in its host_init() callback, which is called during probe. That wait > could possibly just be dropped in favour of the one in > dw_pcie_host_init() and/or the driver could be reworked to implement > start_link(). > > Either way, the call in dw_pcie_host_init() will only add an additional > 1 second delay in cases where the link did *not* come up. > > > As Johan noted, intel-gw should make use of the async probe to avoid the boot > > delay instead of adding a special case. > > Indeed. > > Johan Johan, Mani My apologies for adding this regression in some of the SOCs. May I suggest to keep my patch and make the following change instead? This shall keep the existing behavior as is, and save the boot time for drivers that do not define the start_link()? ``` diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index cf61733bf78d..af6a7cd060b1 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -492,11 +492,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (ret) goto err_remove_edma; - if (pci->ops && pci->ops->start_link) { - ret = dw_pcie_wait_for_link(pci); - if (ret) - goto err_stop_link; - } + if (pci->ops && pci->ops->start_link) + dw_pcie_wait_for_link(pci); } bridge->sysdata = pp; ```