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From: Lukas Wunner <lukas@wunner.de>
To: Wei Huang <wei.huang2@amd.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-doc@vger.kernel.org, netdev@vger.kernel.org,
	Jonathan.Cameron@huawei.com, helgaas@kernel.org, corbet@lwn.net,
	davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
	pabeni@redhat.com, alex.williamson@redhat.com,
	gospo@broadcom.com, michael.chan@broadcom.com,
	ajit.khaparde@broadcom.com, somnath.kotur@broadcom.com,
	andrew.gospodarek@broadcom.com, manoj.panicker2@amd.com,
	Eric.VanTassell@amd.com, vadim.fedorenko@linux.dev,
	horms@kernel.org, bagasdotme@gmail.com, bhelgaas@google.com,
	paul.e.luse@intel.com, jing2.liu@intel.com
Subject: Re: [PATCH V5 1/5] PCI: Add TLP Processing Hints (TPH) support
Date: Mon, 23 Sep 2024 09:43:00 +0200	[thread overview]
Message-ID: <ZvEcBLGqlJMj3MHA@wunner.de> (raw)
In-Reply-To: <20240916205103.3882081-2-wei.huang2@amd.com>

On Mon, Sep 16, 2024 at 03:50:59PM -0500, Wei Huang wrote:
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -1813,6 +1813,7 @@ int pci_save_state(struct pci_dev *dev)
>  	pci_save_dpc_state(dev);
>  	pci_save_aer_state(dev);
>  	pci_save_ptm_state(dev);
> +	pci_save_tph_state(dev);
>  	return pci_save_vc_state(dev);
>  }
>  EXPORT_SYMBOL(pci_save_state);
> @@ -1917,6 +1918,7 @@ void pci_restore_state(struct pci_dev *dev)
>  	pci_restore_vc_state(dev);
>  	pci_restore_rebar_state(dev);
>  	pci_restore_dpc_state(dev);
> +	pci_restore_tph_state(dev);
>  	pci_restore_ptm_state(dev);
>  
>  	pci_aer_clear_status(dev);

I'm wondering if there's a reason to use a different order on save versus
restore?  E.g. does PTM need to be restored last?


> --- a/drivers/pci/pcie/Kconfig
> +++ b/drivers/pci/pcie/Kconfig
> @@ -155,3 +155,14 @@ config PCIE_EDR
>  	  the PCI Firmware Specification r3.2.  Enable this if you want to
>  	  support hybrid DPC model which uses both firmware and OS to
>  	  implement DPC.
> +
> +config PCIE_TPH
> +	bool "TLP Processing Hints"
> +	depends on ACPI

TPH isn't really an ACPI-specific feature, it could exist on
devicetree-based platforms as well.  I think there could be valid
use cases for enabling TPH support on such platforms:

E.g. the platform firmware or bootloader might set up the TPH Extended
Capability in a specific way and the kernel would have to save/restore
it on system sleep.

So I'd recommend removing this dependency.

Note that there's a static inline for acpi_check_dsm() which returns
false if CONFIG_ACPI=n, so tph_invoke_dsm() returns AE_ERROR and
pcie_tph_get_cpu_st() returns -EINVAL.  It thus looks like you may not
even need an #ifdef.


> diff --git a/drivers/pci/pcie/tph.c b/drivers/pci/pcie/tph.c
> new file mode 100644

The PCIe features added most recently (such as DOE) have been placed
directly in drivers/pci/ instead of the pcie/ subdirectory.
The pcie/ subdirectory mostly deals with port drivers.
So perhaps tph.c should likewise be placed in drivers/pci/ ?


> --- /dev/null
> +++ b/drivers/pci/pcie/tph.c
> @@ -0,0 +1,199 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * TPH (TLP Processing Hints) support
> + *
> + * Copyright (C) 2024 Advanced Micro Devices, Inc.
> + *     Eric Van Tassell <Eric.VanTassell@amd.com>
> + *     Wei Huang <wei.huang2@amd.com>
> + */
> +#include <linux/pci.h>
> +#include <linux/pci-acpi.h>

This patch doesn't seem to use any of the symbols defined in pci-acpi.h,
or did I miss anything?  I'd move the inclusion of pci-acpi.h to the patch
that actually uses its symbols.

Thanks,

Lukas

  parent reply	other threads:[~2024-09-23  7:54 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-16 20:50 [PATCH V5 0/5] PCIe TPH and cache direct injection support Wei Huang
2024-09-16 20:50 ` [PATCH V5 1/5] PCI: Add TLP Processing Hints (TPH) support Wei Huang
2024-09-17  7:38   ` Simon Horman
2024-09-23  7:43   ` Lukas Wunner [this message]
2024-09-24 16:34     ` Wei Huang
2024-09-23 12:07   ` Alejandro Lucero Palau
2024-09-23 20:27     ` Wei Huang
2024-09-24 14:33       ` Alejandro Lucero Palau
2024-09-16 20:51 ` [PATCH V5 2/5] PCI/TPH: Add Steering Tag support Wei Huang
2024-09-17  7:32   ` Simon Horman
2024-09-17 14:31     ` Wei Huang
2024-09-17 16:14       ` Simon Horman
2024-09-17 16:24         ` Simon Horman
2024-09-20 10:38   ` kernel test robot
2024-09-16 20:51 ` [PATCH V5 3/5] PCI/TPH: Add TPH documentation Wei Huang
2024-09-16 20:51 ` [PATCH V5 4/5] bnxt_en: Add TPH support in BNXT driver Wei Huang
2024-09-16 21:25   ` Wei Huang
2024-09-23  7:25     ` Lukas Wunner
2024-09-23 20:16       ` Wei Huang
2024-09-17  7:35   ` Simon Horman
2024-09-20 10:38   ` kernel test robot
2024-09-16 20:51 ` [PATCH V5 5/5] bnxt_en: Pass NQ ID to the FW when allocating RX/RX AGG rings Wei Huang

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