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Thu, 31 Oct 2024 13:25:28 -0700 (PDT) Received: from fan ([2601:646:8f03:9fee:1a14:7759:606e:c90]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211057bfd09sm12324315ad.183.2024.10.31.13.25.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Oct 2024 13:25:27 -0700 (PDT) From: Fan Ni X-Google-Original-From: Fan Ni Date: Thu, 31 Oct 2024 13:25:24 -0700 To: Terry Bowman Cc: ming4.li@intel.com, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, dan.j.williams@intel.com, bhelgaas@google.com, mahesh@linux.ibm.com, ira.weiny@intel.com, oohall@gmail.com, Benjamin.Cheatham@amd.com, rrichter@amd.com, nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com Subject: Re: [PATCH v2 02/14] PCI/AER: Rename AER driver's interfaces to also indicate CXL PCIe port support Message-ID: References: <20241025210305.27499-1-terry.bowman@amd.com> <20241025210305.27499-3-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241025210305.27499-3-terry.bowman@amd.com> On Fri, Oct 25, 2024 at 04:02:53PM -0500, Terry Bowman wrote: > The AER service driver already includes support for CXL restricted host > (RCH) downstream port error handling. The current implementation is based > on CXL1.1 using a root complex event collector. > > Rename function interfaces and parameters where necessary to include > virtual hierarchy (VH) mode CXL PCIe port error handling alongside the RCH > handling.[1] The CXL PCIe port error handling will be added in a future > patch. > > Limit changes to renaming variable and function names. No functional > changes are added. > > [1] CXL 3.1 Spec, 9.12.2 CXL Virtual Hierarchy > > Signed-off-by: Terry Bowman Reviewed-by: Fan Ni > --- > drivers/pci/pcie/aer.c | 28 ++++++++++++++-------------- > 1 file changed, 14 insertions(+), 14 deletions(-) > > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > index 13b8586924ea..fe6edf26279e 100644 > --- a/drivers/pci/pcie/aer.c > +++ b/drivers/pci/pcie/aer.c > @@ -1029,7 +1029,7 @@ static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) > return 0; > } > > -static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) > +static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) > { > /* > * Internal errors of an RCEC indicate an AER error in an > @@ -1052,30 +1052,30 @@ static int handles_cxl_error_iter(struct pci_dev *dev, void *data) > return *handles_cxl; > } > > -static bool handles_cxl_errors(struct pci_dev *rcec) > +static bool handles_cxl_errors(struct pci_dev *dev) > { > bool handles_cxl = false; > > - if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC && > - pcie_aer_is_native(rcec)) > - pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); > + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && > + pcie_aer_is_native(dev)) > + pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); > > return handles_cxl; > } > > -static void cxl_rch_enable_rcec(struct pci_dev *rcec) > +static void cxl_enable_internal_errors(struct pci_dev *dev) > { > - if (!handles_cxl_errors(rcec)) > + if (!handles_cxl_errors(dev)) > return; > > - pci_aer_unmask_internal_errors(rcec); > - pci_info(rcec, "CXL: Internal errors unmasked"); > + pci_aer_unmask_internal_errors(dev); > + pci_info(dev, "CXL: Internal errors unmasked"); > } > > #else > -static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } > -static inline void cxl_rch_handle_error(struct pci_dev *dev, > - struct aer_err_info *info) { } > +static inline void cxl_enable_internal_errors(struct pci_dev *dev) { } > +static inline void cxl_handle_error(struct pci_dev *dev, > + struct aer_err_info *info) { } > #endif > > /** > @@ -1113,7 +1113,7 @@ static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info) > > static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) > { > - cxl_rch_handle_error(dev, info); > + cxl_handle_error(dev, info); > pci_aer_handle_error(dev, info); > pci_dev_put(dev); > } > @@ -1491,7 +1491,7 @@ static int aer_probe(struct pcie_device *dev) > return status; > } > > - cxl_rch_enable_rcec(port); > + cxl_enable_internal_errors(port); > aer_enable_rootport(rpc); > pci_info(port, "enabled with IRQ %d\n", dev->irq); > return 0; > -- > 2.34.1 > -- Fan Ni