Re: [PATCH v5 14/16] cxl/pci: Add trace logging for CXL PCIe Port RAS errors

Jonathan Cameron
2025-01-15T11:42:22Z

> >> diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
> >> index 8389a94adb1a..681e415ac8f5 100644
> >> --- a/drivers/cxl/core/trace.h
> >> +++ b/drivers/cxl/core/trace.h
> >> @@ -48,6 +48,34 @@
> >> { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \
> >> )
> >>
> >> +TRACE_EVENT(cxl_port_aer_uncorrectable_error,
> >> + TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl),
> >> + TP_ARGS(dev, status, fe, hl),
> >> + TP_STRUCT__entry(
> >> + __string(devname, dev_name(dev))
> >> + __string(host, dev_name(dev->parent))
> > What is host in this case? Perhaps a comment.
> host is a string initialized with value from dev_name(dev->parent). What
> kind of comment would you like to see here?
What is that parent in practice? A port, an EP, a PCI device?

>
> Regards,
> Terry