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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Shradha Todi <shradha.t@samsung.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.or, linux-kernel@vger.kernel.org,
	linux-phy@lists.infradead.org, manivannan.sadhasivam@linaro.org,
	lpieralisi@kernel.org, kw@linux.com, robh@kernel.org,
	bhelgaas@google.com, jingoohan1@gmail.com, krzk+dt@kernel.org,
	conor+dt@kernel.org, alim.akhtar@samsung.com, vkoul@kernel.org,
	kishon@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com,
	jh80.chung@samsung.com
Subject: Re: [PATCH 08/10] phy: exynos: Add PCIe PHY support for FSD SoC
Date: Wed, 28 May 2025 09:21:27 +0200	[thread overview]
Message-ID: <a42f7c93-4c26-489e-a680-ad20a8b8a0a6@kernel.org> (raw)
In-Reply-To: <0e2701dbcef4$6f5f24d0$4e1d6e70$@samsung.com>

On 27/05/2025 12:45, Shradha Todi wrote:
>>>
>>> -	generic_phy = devm_phy_create(dev, dev->of_node, &exynos5433_phy_ops);
>>> +	generic_phy = devm_phy_create(dev, dev->of_node, drv_data->phy_ops);
>>>  	if (IS_ERR(generic_phy)) {
>>>  		dev_err(dev, "failed to create PHY\n");
>>>  		return PTR_ERR(generic_phy);
>>>  	}
>>>
>>> +	exynos_phy->pcs_base = devm_platform_ioremap_resource(pdev, 1);
>>> +	exynos_phy->phy_id = of_alias_get_id(dev->of_node, "pciephy");
>>
>> Where did you document aliases?
>>
> 
> Will add it to dt bindings.
> 
>> Anyway, all this looks because you have completely buggy way of handling MMIO via syscon. That's a no-go. Use proper address
>> ranges assigned to ddevices. If you ever need to use syscon, you should pass the offset as argument - just like other devices are
>> doing.
>>
> 
> Alias is used for 2 reasons.

So if on my board the PCI slots are named differently and I use
different alias, everything will stop working, right? Usually aliases
for exposable buses are matching what is physically labeled on the
exposed interface.

> 1. Each of the 2 PHYs in FSD have different initializing sequence due to channel length, etc. We need the alias to select the init sequence accordingly

So devices are different? What is channel length? Number of lanes?


> 2. The syscon offset can be passed via DT but the bit field also varies according to instance. (common reset is bit 8 in PHY0 and bit 1 in PHY1).

You did not address the main problem here: you use MMIO but do not
define any MMIO. Syscon is not a replacement for MMIO.


Best regards,
Krzysztof

  reply	other threads:[~2025-05-28  7:21 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20250518193219epcas5p24b442233b3e2bc2a92f43b71a126062f@epcas5p2.samsung.com>
2025-05-18 19:31 ` [PATCH 00/10] Add PCIe support for Tesla FSD SoC Shradha Todi
     [not found]   ` <CGME20250518193221epcas5p3c648c773d901f18639dd32fa452fd688@epcas5p3.samsung.com>
2025-05-18 19:31     ` [PATCH 01/10] PCI: exynos: Change macro names to exynos specific Shradha Todi
     [not found]   ` <CGME20250518193230epcas5p3dfb178a6528556c55e9b694ca8f8ad6c@epcas5p3.samsung.com>
2025-05-18 19:31     ` [PATCH 02/10] PCI: exynos: Remove unused MACROs in exynos PCI file Shradha Todi
2025-05-21  9:41       ` Krzysztof Kozlowski
2025-05-27 10:42         ` Shradha Todi
     [not found]   ` <CGME20250518193235epcas5p4f0bcf581b583a3acf493a20191ad2b00@epcas5p4.samsung.com>
2025-05-18 19:31     ` [PATCH 03/10] PCI: exynos: Reorder MACROs to maintain consistency Shradha Todi
2025-05-21  9:45       ` Krzysztof Kozlowski
2025-05-27 10:42         ` Shradha Todi
     [not found]   ` <CGME20250518193239epcas5p4cb4112382560f38ad9708e000eb2335f@epcas5p4.samsung.com>
2025-05-18 19:31     ` [PATCH 04/10] PCI: exynos: Add platform device private data Shradha Todi
2025-05-21  9:44       ` Krzysztof Kozlowski
2025-05-27 10:43         ` Shradha Todi
2025-06-13  9:04           ` Manivannan Sadhasivam
     [not found]   ` <CGME20250518193244epcas5p3cacfbdc3b0e5c32f7a4dd97062a931a4@epcas5p3.samsung.com>
2025-05-18 19:31     ` [PATCH 05/10] PCI: exynos: Add structure to hold resource operations Shradha Todi
2025-05-21  9:42       ` Krzysztof Kozlowski
2025-05-27 10:44         ` Shradha Todi
     [not found]   ` <CGME20250518193248epcas5p2543146c715eb249ea6c2ce3c78d03b34@epcas5p2.samsung.com>
2025-05-18 19:31     ` [PATCH 06/10] dt-bindings: PCI: Add bindings support for Tesla FSD SoC Shradha Todi
2025-05-21  9:37       ` Krzysztof Kozlowski
2025-05-27 10:44         ` Shradha Todi
     [not found]   ` <CGME20250518193252epcas5p3e4d1d329f1e5616e842801ceb26728b6@epcas5p3.samsung.com>
2025-05-18 19:31     ` [PATCH 07/10] dt-bindings: phy: Add PHY bindings support for " Shradha Todi
2025-05-21  9:33       ` Krzysztof Kozlowski
2025-05-27 10:44         ` Shradha Todi
     [not found]   ` <CGME20250518193256epcas5p442e9549fd8fd810522f960df74c22e34@epcas5p4.samsung.com>
2025-05-18 19:31     ` [PATCH 08/10] phy: exynos: Add PCIe PHY " Shradha Todi
2025-05-21  9:40       ` Krzysztof Kozlowski
2025-05-27 10:45         ` Shradha Todi
2025-05-28  7:21           ` Krzysztof Kozlowski [this message]
     [not found]   ` <CGME20250518193300epcas5p17e954bb18de9169d65e00501b1dcd046@epcas5p1.samsung.com>
2025-05-18 19:31     ` [PATCH 09/10] PCI: exynos: Add support for Tesla " Shradha Todi
2025-05-19 10:26       ` Niklas Cassel
2025-05-21  9:48       ` Krzysztof Kozlowski
2025-05-27 10:45         ` Shradha Todi
2025-05-28  7:25           ` Krzysztof Kozlowski
2025-05-29 10:24             ` Shradha Todi
     [not found]   ` <CGME20250518193305epcas5p263b59196e93ef504eab8537f82c37342@epcas5p2.samsung.com>
2025-05-18 19:31     ` [PATCH 10/10] misc: pci_endpoint_test: Add driver data for FSD PCIe controllers Shradha Todi
2025-05-19  9:59       ` Niklas Cassel

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