* [PATCHv2 1/6] PCI: designware: add accessors for write permission of DBI read-only registers
2017-08-03 8:23 [PATCHv2 0/6] PCI: fix the designware Class code fixup doesn't work issue and refactor ls-pcie host init Zhiqiang Hou
@ 2017-08-03 8:23 ` Zhiqiang Hou
2017-08-08 12:45 ` Joao Pinto
2017-08-03 8:23 ` [PATCHv2 2/6] PCI: designware: enable write permission before updating class code Zhiqiang Hou
` (4 subsequent siblings)
5 siblings, 1 reply; 21+ messages in thread
From: Zhiqiang Hou @ 2017-08-03 8:23 UTC (permalink / raw)
To: linux-pci, bhelgaas, jingoohan1, Joao.Pinto
Cc: minghuan.lian, mingkai.hu, roy.zang, Hou Zhiqiang
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The read-only DBI registers can be written over the DBI when set
the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the
MISC_CONTROL_1_OFF register.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- None
drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index b4d2a89..bbdf35b 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -76,6 +76,9 @@
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET 0x91C
+#define PCIE_MISC_CONTROL_1_OFF 0x8BC
+#define PCIE_DBI_RO_WR_EN (0x1 << 0)
+
/*
* iATU Unroll-specific register definitions
* From 4.80 core version the address translation will be made by unroll
@@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
}
+static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
+{
+ u32 reg;
+ u32 val;
+
+ reg = PCIE_MISC_CONTROL_1_OFF;
+ val = dw_pcie_readl_dbi(pci, reg);
+ val |= PCIE_DBI_RO_WR_EN;
+ dw_pcie_writel_dbi(pci, reg, val);
+}
+
+static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
+{
+ u32 reg;
+ u32 val;
+
+ reg = PCIE_MISC_CONTROL_1_OFF;
+ val = dw_pcie_readl_dbi(pci, reg);
+ val &= ~PCIE_DBI_RO_WR_EN;
+ dw_pcie_writel_dbi(pci, reg, val);
+}
+
#ifdef CONFIG_PCIE_DW_HOST
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
void dw_pcie_msi_init(struct pcie_port *pp);
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCHv2 1/6] PCI: designware: add accessors for write permission of DBI read-only registers
2017-08-03 8:23 ` [PATCHv2 1/6] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou
@ 2017-08-08 12:45 ` Joao Pinto
2017-08-09 2:50 ` Z.q. Hou
0 siblings, 1 reply; 21+ messages in thread
From: Joao Pinto @ 2017-08-08 12:45 UTC (permalink / raw)
To: Zhiqiang Hou, linux-pci, bhelgaas, jingoohan1, Joao.Pinto
Cc: minghuan.lian, mingkai.hu, roy.zang
Às 9:23 AM de 8/3/2017, Zhiqiang Hou escreveu:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> The read-only DBI registers can be written over the DBI when set
> the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the
> MISC_CONTROL_1_OFF register.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V2:
> - None
>
> drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
> index b4d2a89..bbdf35b 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -76,6 +76,9 @@
> #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
> #define PCIE_ATU_UPPER_TARGET 0x91C
>
> +#define PCIE_MISC_CONTROL_1_OFF 0x8BC
> +#define PCIE_DBI_RO_WR_EN (0x1 << 0)
> +
> /*
> * iATU Unroll-specific register definitions
> * From 4.80 core version the address translation will be made by unroll
> @@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
> return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
> }
>
> +static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
> +{
> + u32 reg;
> + u32 val;
> +
> + reg = PCIE_MISC_CONTROL_1_OFF;
> + val = dw_pcie_readl_dbi(pci, reg);
> + val |= PCIE_DBI_RO_WR_EN;
> + dw_pcie_writel_dbi(pci, reg, val);
> +}
> +
> +static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
> +{
> + u32 reg;
> + u32 val;
> +
> + reg = PCIE_MISC_CONTROL_1_OFF;
> + val = dw_pcie_readl_dbi(pci, reg);
> + val &= ~PCIE_DBI_RO_WR_EN;
> + dw_pcie_writel_dbi(pci, reg, val);
> +}
> +
> #ifdef CONFIG_PCIE_DW_HOST
> irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
> void dw_pcie_msi_init(struct pcie_port *pp);
>
Acked-By: Joao Pinto <jpinto@synopsys.com>
^ permalink raw reply [flat|nested] 21+ messages in thread* RE: [PATCHv2 1/6] PCI: designware: add accessors for write permission of DBI read-only registers
2017-08-08 12:45 ` Joao Pinto
@ 2017-08-09 2:50 ` Z.q. Hou
0 siblings, 0 replies; 21+ messages in thread
From: Z.q. Hou @ 2017-08-09 2:50 UTC (permalink / raw)
To: Joao Pinto, linux-pci@vger.kernel.org, bhelgaas@google.com,
jingoohan1@gmail.com
Cc: M.h. Lian, Mingkai Hu, Roy Zang
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^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCHv2 2/6] PCI: designware: enable write permission before updating class code
2017-08-03 8:23 [PATCHv2 0/6] PCI: fix the designware Class code fixup doesn't work issue and refactor ls-pcie host init Zhiqiang Hou
2017-08-03 8:23 ` [PATCHv2 1/6] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou
@ 2017-08-03 8:23 ` Zhiqiang Hou
2017-08-08 12:45 ` Joao Pinto
2017-08-03 8:23 ` [PATCHv2 3/6] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission Zhiqiang Hou
` (3 subsequent siblings)
5 siblings, 1 reply; 21+ messages in thread
From: Zhiqiang Hou @ 2017-08-03 8:23 UTC (permalink / raw)
To: linux-pci, bhelgaas, jingoohan1, Joao.Pinto
Cc: minghuan.lian, mingkai.hu, roy.zang, Hou Zhiqiang
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The existing fix doesn't actually work because the Class register is
read-only, so it must enable the write permission before write the
correct value to this register.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- None
drivers/pci/dwc/pcie-designware-host.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index d29c020..6e10cda 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -634,8 +634,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
+ /* Enable write permission for the DBI read-only register */
+ dw_pcie_dbi_ro_wr_en(pci);
/* program correct class for RC */
dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+ /* Better disable write permission right after the update */
+ dw_pcie_dbi_ro_wr_dis(pci);
dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
val |= PORT_LOGIC_SPEED_CHANGE;
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCHv2 2/6] PCI: designware: enable write permission before updating class code
2017-08-03 8:23 ` [PATCHv2 2/6] PCI: designware: enable write permission before updating class code Zhiqiang Hou
@ 2017-08-08 12:45 ` Joao Pinto
2017-08-09 2:51 ` Z.q. Hou
0 siblings, 1 reply; 21+ messages in thread
From: Joao Pinto @ 2017-08-08 12:45 UTC (permalink / raw)
To: Zhiqiang Hou, linux-pci, bhelgaas, jingoohan1, Joao.Pinto
Cc: minghuan.lian, mingkai.hu, roy.zang
Às 9:23 AM de 8/3/2017, Zhiqiang Hou escreveu:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> The existing fix doesn't actually work because the Class register is
> read-only, so it must enable the write permission before write the
> correct value to this register.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V2:
> - None
>
> drivers/pci/dwc/pcie-designware-host.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
> index d29c020..6e10cda 100644
> --- a/drivers/pci/dwc/pcie-designware-host.c
> +++ b/drivers/pci/dwc/pcie-designware-host.c
> @@ -634,8 +634,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>
> dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
>
> + /* Enable write permission for the DBI read-only register */
> + dw_pcie_dbi_ro_wr_en(pci);
> /* program correct class for RC */
> dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
> + /* Better disable write permission right after the update */
> + dw_pcie_dbi_ro_wr_dis(pci);
>
> dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
> val |= PORT_LOGIC_SPEED_CHANGE;
>
Acked-By: Joao Pinto <jpinto@synopsys.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [PATCHv2 2/6] PCI: designware: enable write permission before updating class code
2017-08-08 12:45 ` Joao Pinto
@ 2017-08-09 2:51 ` Z.q. Hou
0 siblings, 0 replies; 21+ messages in thread
From: Z.q. Hou @ 2017-08-09 2:51 UTC (permalink / raw)
To: Joao Pinto, linux-pci@vger.kernel.org, bhelgaas@google.com,
jingoohan1@gmail.com
Cc: M.h. Lian, Mingkai Hu, Roy Zang
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ICsJZHdfcGNpZV9kYmlfcm9fd3JfZGlzKHBjaSk7DQo+ID4NCj4gPiAgCWR3X3BjaWVfcmRfb3du
X2NvbmYocHAsIFBDSUVfTElOS19XSURUSF9TUEVFRF9DT05UUk9MLCA0LA0KPiAmdmFsKTsNCj4g
PiAgCXZhbCB8PSBQT1JUX0xPR0lDX1NQRUVEX0NIQU5HRTsNCj4gPg0KPiANCj4gQWNrZWQtQnk6
IEpvYW8gUGludG8gPGpwaW50b0BzeW5vcHN5cy5jb20+DQoNCi0gWmhpcWlhbmcNCg==
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCHv2 3/6] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission
2017-08-03 8:23 [PATCHv2 0/6] PCI: fix the designware Class code fixup doesn't work issue and refactor ls-pcie host init Zhiqiang Hou
2017-08-03 8:23 ` [PATCHv2 1/6] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou
2017-08-03 8:23 ` [PATCHv2 2/6] PCI: designware: enable write permission before updating class code Zhiqiang Hou
@ 2017-08-03 8:23 ` Zhiqiang Hou
2017-08-08 12:46 ` Joao Pinto
2017-08-03 8:23 ` [PATCHv2 4/6] PCI: layerscape: refactor the host_init function Zhiqiang Hou
` (2 subsequent siblings)
5 siblings, 1 reply; 21+ messages in thread
From: Zhiqiang Hou @ 2017-08-03 8:23 UTC (permalink / raw)
To: linux-pci, bhelgaas, jingoohan1, Joao.Pinto
Cc: minghuan.lian, mingkai.hu, roy.zang, Hou Zhiqiang
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Use the accessors instead accessing the DBI read-only write enable
register directly. And the STRFMR1 is not read-only register, so move it
out from the write-enable bracket.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- New patch split from patch v1 3/3.
drivers/pci/dwc/pci-layerscape.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index fd86128..09056a6 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -33,7 +33,6 @@
/* PEX Internal Configuration Registers */
#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
-#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
struct ls_pcie_drvdata {
u32 lut_offset;
@@ -155,11 +154,12 @@ static void ls_pcie_host_init(struct pcie_port *pp)
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct ls_pcie *pcie = to_ls_pcie(pci);
- iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
+ dw_pcie_dbi_ro_wr_en(pci);
ls_pcie_fix_class(pcie);
ls_pcie_clear_multifunction(pcie);
+ dw_pcie_dbi_ro_wr_dis(pci);
+
ls_pcie_drop_msg_tlp(pcie);
- iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
}
static int ls_pcie_msi_host_init(struct pcie_port *pp,
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCHv2 3/6] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission
2017-08-03 8:23 ` [PATCHv2 3/6] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission Zhiqiang Hou
@ 2017-08-08 12:46 ` Joao Pinto
2017-08-09 2:52 ` Z.q. Hou
0 siblings, 1 reply; 21+ messages in thread
From: Joao Pinto @ 2017-08-08 12:46 UTC (permalink / raw)
To: Zhiqiang Hou, linux-pci, bhelgaas, jingoohan1, Joao.Pinto
Cc: minghuan.lian, mingkai.hu, roy.zang
Às 9:23 AM de 8/3/2017, Zhiqiang Hou escreveu:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> Use the accessors instead accessing the DBI read-only write enable
> register directly. And the STRFMR1 is not read-only register, so move it
> out from the write-enable bracket.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V2:
> - New patch split from patch v1 3/3.
>
> drivers/pci/dwc/pci-layerscape.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
> index fd86128..09056a6 100644
> --- a/drivers/pci/dwc/pci-layerscape.c
> +++ b/drivers/pci/dwc/pci-layerscape.c
> @@ -33,7 +33,6 @@
>
> /* PEX Internal Configuration Registers */
> #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
> -#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
>
> struct ls_pcie_drvdata {
> u32 lut_offset;
> @@ -155,11 +154,12 @@ static void ls_pcie_host_init(struct pcie_port *pp)
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> struct ls_pcie *pcie = to_ls_pcie(pci);
>
> - iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
> + dw_pcie_dbi_ro_wr_en(pci);
> ls_pcie_fix_class(pcie);
> ls_pcie_clear_multifunction(pcie);
> + dw_pcie_dbi_ro_wr_dis(pci);
> +
> ls_pcie_drop_msg_tlp(pcie);
> - iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
> }
>
> static int ls_pcie_msi_host_init(struct pcie_port *pp,
>
Acked-By: Joao Pinto <jpinto@synopsys.com>
^ permalink raw reply [flat|nested] 21+ messages in thread* RE: [PATCHv2 3/6] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission
2017-08-08 12:46 ` Joao Pinto
@ 2017-08-09 2:52 ` Z.q. Hou
0 siblings, 0 replies; 21+ messages in thread
From: Z.q. Hou @ 2017-08-09 2:52 UTC (permalink / raw)
To: Joao Pinto, linux-pci@vger.kernel.org, bhelgaas@google.com,
jingoohan1@gmail.com
Cc: M.h. Lian, Mingkai Hu, Roy Zang
SGkgSm9hbywNCg0KVGhhbmtzIGEgbG90IGZvciB5b3VyIGFjayENCg0KPiAtLS0tLU9yaWdpbmFs
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ID4NCj4gPiAgc3RhdGljIGludCBsc19wY2llX21zaV9ob3N0X2luaXQoc3RydWN0IHBjaWVfcG9y
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Y29tPg0KDQotIFpoaXFpYW5nDQo=
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCHv2 4/6] PCI: layerscape: refactor the host_init function
2017-08-03 8:23 [PATCHv2 0/6] PCI: fix the designware Class code fixup doesn't work issue and refactor ls-pcie host init Zhiqiang Hou
` (2 preceding siblings ...)
2017-08-03 8:23 ` [PATCHv2 3/6] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission Zhiqiang Hou
@ 2017-08-03 8:23 ` Zhiqiang Hou
2017-08-08 13:13 ` Joao Pinto
2017-08-14 21:38 ` Bjorn Helgaas
2017-08-03 8:23 ` [PATCHv2 5/6] PCI: layerscape: Disable the outbound windows configured by bootloader Zhiqiang Hou
2017-08-03 8:23 ` [PATCHv2 6/6] PCI: layerscape: remove the duplicate Class field fix code Zhiqiang Hou
5 siblings, 2 replies; 21+ messages in thread
From: Zhiqiang Hou @ 2017-08-03 8:23 UTC (permalink / raw)
To: linux-pci, bhelgaas, jingoohan1, Joao.Pinto
Cc: minghuan.lian, mingkai.hu, roy.zang, Hou Zhiqiang
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Make the ls1021a's host_init reuse layerscape platform's common
host_init function.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- Removed the disable outbound windows code and the remove duplicate class code
fixup code from this patch.
drivers/pci/dwc/pci-layerscape.c | 54 ++++++++++++++++++++--------------------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 09056a6..3533a8c 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -107,33 +107,6 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci)
return 1;
}
-static void ls1021_pcie_host_init(struct pcie_port *pp)
-{
- struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct ls_pcie *pcie = to_ls_pcie(pci);
- struct device *dev = pci->dev;
- u32 index[2];
-
- pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
- "fsl,pcie-scfg");
- if (IS_ERR(pcie->scfg)) {
- dev_err(dev, "No syscfg phandle specified\n");
- pcie->scfg = NULL;
- return;
- }
-
- if (of_property_read_u32_array(dev->of_node,
- "fsl,pcie-scfg", index, 2)) {
- pcie->scfg = NULL;
- return;
- }
- pcie->index = index[1];
-
- dw_pcie_setup_rc(pp);
-
- ls_pcie_drop_msg_tlp(pcie);
-}
-
static int ls_pcie_link_up(struct dw_pcie *pci)
{
struct ls_pcie *pcie = to_ls_pcie(pci);
@@ -160,6 +133,33 @@ static void ls_pcie_host_init(struct pcie_port *pp)
dw_pcie_dbi_ro_wr_dis(pci);
ls_pcie_drop_msg_tlp(pcie);
+
+ dw_pcie_setup_rc(pp);
+}
+
+static void ls1021_pcie_host_init(struct pcie_port *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct ls_pcie *pcie = to_ls_pcie(pci);
+ struct device *dev = pci->dev;
+ u32 index[2];
+
+ pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "fsl,pcie-scfg");
+ if (IS_ERR(pcie->scfg)) {
+ dev_err(dev, "No syscfg phandle specified\n");
+ pcie->scfg = NULL;
+ return;
+ }
+
+ if (of_property_read_u32_array(dev->of_node,
+ "fsl,pcie-scfg", index, 2)) {
+ pcie->scfg = NULL;
+ return;
+ }
+ pcie->index = index[1];
+
+ ls_pcie_host_init(pp);
}
static int ls_pcie_msi_host_init(struct pcie_port *pp,
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCHv2 4/6] PCI: layerscape: refactor the host_init function
2017-08-03 8:23 ` [PATCHv2 4/6] PCI: layerscape: refactor the host_init function Zhiqiang Hou
@ 2017-08-08 13:13 ` Joao Pinto
2017-08-09 2:53 ` Z.q. Hou
2017-08-14 21:38 ` Bjorn Helgaas
1 sibling, 1 reply; 21+ messages in thread
From: Joao Pinto @ 2017-08-08 13:13 UTC (permalink / raw)
To: Zhiqiang Hou, linux-pci, bhelgaas, jingoohan1, Joao.Pinto
Cc: minghuan.lian, mingkai.hu, roy.zang
Às 9:23 AM de 8/3/2017, Zhiqiang Hou escreveu:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> Make the ls1021a's host_init reuse layerscape platform's common
> host_init function.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V2:
> - Removed the disable outbound windows code and the remove duplicate class code
> fixup code from this patch.
>
> drivers/pci/dwc/pci-layerscape.c | 54 ++++++++++++++++++++--------------------
> 1 file changed, 27 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
> index 09056a6..3533a8c 100644
> --- a/drivers/pci/dwc/pci-layerscape.c
> +++ b/drivers/pci/dwc/pci-layerscape.c
> @@ -107,33 +107,6 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci)
> return 1;
> }
>
> -static void ls1021_pcie_host_init(struct pcie_port *pp)
> -{
> - struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> - struct ls_pcie *pcie = to_ls_pcie(pci);
> - struct device *dev = pci->dev;
> - u32 index[2];
> -
> - pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
> - "fsl,pcie-scfg");
> - if (IS_ERR(pcie->scfg)) {
> - dev_err(dev, "No syscfg phandle specified\n");
> - pcie->scfg = NULL;
> - return;
> - }
> -
> - if (of_property_read_u32_array(dev->of_node,
> - "fsl,pcie-scfg", index, 2)) {
> - pcie->scfg = NULL;
> - return;
> - }
> - pcie->index = index[1];
> -
> - dw_pcie_setup_rc(pp);
> -
> - ls_pcie_drop_msg_tlp(pcie);
> -}
> -
> static int ls_pcie_link_up(struct dw_pcie *pci)
> {
> struct ls_pcie *pcie = to_ls_pcie(pci);
> @@ -160,6 +133,33 @@ static void ls_pcie_host_init(struct pcie_port *pp)
> dw_pcie_dbi_ro_wr_dis(pci);
>
> ls_pcie_drop_msg_tlp(pcie);
> +
> + dw_pcie_setup_rc(pp);
> +}
> +
> +static void ls1021_pcie_host_init(struct pcie_port *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct ls_pcie *pcie = to_ls_pcie(pci);
> + struct device *dev = pci->dev;
> + u32 index[2];
> +
> + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
> + "fsl,pcie-scfg");
> + if (IS_ERR(pcie->scfg)) {
> + dev_err(dev, "No syscfg phandle specified\n");
> + pcie->scfg = NULL;
> + return;
> + }
> +
> + if (of_property_read_u32_array(dev->of_node,
> + "fsl,pcie-scfg", index, 2)) {
> + pcie->scfg = NULL;
> + return;
> + }
> + pcie->index = index[1];
> +
> + ls_pcie_host_init(pp);
> }
>
> static int ls_pcie_msi_host_init(struct pcie_port *pp,
>
Reviewed-by: Joao Pinto <jpinto@synopsys.com>
^ permalink raw reply [flat|nested] 21+ messages in thread* RE: [PATCHv2 4/6] PCI: layerscape: refactor the host_init function
2017-08-08 13:13 ` Joao Pinto
@ 2017-08-09 2:53 ` Z.q. Hou
0 siblings, 0 replies; 21+ messages in thread
From: Z.q. Hou @ 2017-08-09 2:53 UTC (permalink / raw)
To: Joao Pinto, linux-pci@vger.kernel.org, bhelgaas@google.com,
jingoohan1@gmail.com
Cc: M.h. Lian, Mingkai Hu, Roy Zang
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCHv2 4/6] PCI: layerscape: refactor the host_init function
2017-08-03 8:23 ` [PATCHv2 4/6] PCI: layerscape: refactor the host_init function Zhiqiang Hou
2017-08-08 13:13 ` Joao Pinto
@ 2017-08-14 21:38 ` Bjorn Helgaas
2017-08-14 22:26 ` Bjorn Helgaas
2017-08-15 3:05 ` Z.q. Hou
1 sibling, 2 replies; 21+ messages in thread
From: Bjorn Helgaas @ 2017-08-14 21:38 UTC (permalink / raw)
To: Zhiqiang Hou
Cc: linux-pci, bhelgaas, jingoohan1, Joao.Pinto, minghuan.lian,
mingkai.hu, roy.zang
On Thu, Aug 03, 2017 at 04:23:38PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> Make the ls1021a's host_init reuse layerscape platform's common
> host_init function.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V2:
> - Removed the disable outbound windows code and the remove duplicate class code
> fixup code from this patch.
>
> drivers/pci/dwc/pci-layerscape.c | 54 ++++++++++++++++++++--------------------
> 1 file changed, 27 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
> index 09056a6..3533a8c 100644
> --- a/drivers/pci/dwc/pci-layerscape.c
> +++ b/drivers/pci/dwc/pci-layerscape.c
> @@ -107,33 +107,6 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci)
> return 1;
> }
>
> -static void ls1021_pcie_host_init(struct pcie_port *pp)
> -{
> - struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> - struct ls_pcie *pcie = to_ls_pcie(pci);
> - struct device *dev = pci->dev;
> - u32 index[2];
> -
> - pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
> - "fsl,pcie-scfg");
> - if (IS_ERR(pcie->scfg)) {
> - dev_err(dev, "No syscfg phandle specified\n");
> - pcie->scfg = NULL;
> - return;
> - }
> -
> - if (of_property_read_u32_array(dev->of_node,
> - "fsl,pcie-scfg", index, 2)) {
> - pcie->scfg = NULL;
> - return;
> - }
> - pcie->index = index[1];
> -
> - dw_pcie_setup_rc(pp);
> -
> - ls_pcie_drop_msg_tlp(pcie);
> -}
> -
> static int ls_pcie_link_up(struct dw_pcie *pci)
> {
> struct ls_pcie *pcie = to_ls_pcie(pci);
> @@ -160,6 +133,33 @@ static void ls_pcie_host_init(struct pcie_port *pp)
> dw_pcie_dbi_ro_wr_dis(pci);
>
> ls_pcie_drop_msg_tlp(pcie);
> +
> + dw_pcie_setup_rc(pp);
> +}
> +
> +static void ls1021_pcie_host_init(struct pcie_port *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct ls_pcie *pcie = to_ls_pcie(pci);
> + struct device *dev = pci->dev;
> + u32 index[2];
> +
> + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
> + "fsl,pcie-scfg");
> + if (IS_ERR(pcie->scfg)) {
> + dev_err(dev, "No syscfg phandle specified\n");
> + pcie->scfg = NULL;
> + return;
> + }
> +
> + if (of_property_read_u32_array(dev->of_node,
> + "fsl,pcie-scfg", index, 2)) {
> + pcie->scfg = NULL;
> + return;
> + }
> + pcie->index = index[1];
> +
> + ls_pcie_host_init(pp);
The changelog suggests that this is a simple refactoring that doesn't
fix anything.
But because ls1021_pcie_host_init() now calls ls_pcie_host_init(), it
now calls:
dw_pcie_dbi_ro_wr_en(pci);
ls_pcie_fix_class(pcie);
ls_pcie_clear_multifunction(pcie);
dw_pcie_dbi_ro_wr_dis(pci);
when it did not call them before.
It's fine with me if you want to do that, but it should be mentioned
in the changelog.
> }
>
> static int ls_pcie_msi_host_init(struct pcie_port *pp,
> --
> 2.1.0.27.g96db324
>
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCHv2 4/6] PCI: layerscape: refactor the host_init function
2017-08-14 21:38 ` Bjorn Helgaas
@ 2017-08-14 22:26 ` Bjorn Helgaas
2017-08-15 3:21 ` Z.q. Hou
2017-08-15 9:34 ` Stanimir Varbanov
2017-08-15 3:05 ` Z.q. Hou
1 sibling, 2 replies; 21+ messages in thread
From: Bjorn Helgaas @ 2017-08-14 22:26 UTC (permalink / raw)
To: Zhiqiang Hou
Cc: linux-pci, bhelgaas, jingoohan1, Joao.Pinto, minghuan.lian,
mingkai.hu, roy.zang, Stanimir Varbanov, Niklas Cassel,
Jesper Nilsson
[+cc Stanimir, Niklas, Jesper]
On Mon, Aug 14, 2017 at 04:38:24PM -0500, Bjorn Helgaas wrote:
> On Thu, Aug 03, 2017 at 04:23:38PM +0800, Zhiqiang Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Make the ls1021a's host_init reuse layerscape platform's common
> > host_init function.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> > V2:
> > - Removed the disable outbound windows code and the remove duplicate class code
> > fixup code from this patch.
> >
> > drivers/pci/dwc/pci-layerscape.c | 54 ++++++++++++++++++++--------------------
> > 1 file changed, 27 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
> > index 09056a6..3533a8c 100644
> > --- a/drivers/pci/dwc/pci-layerscape.c
> > +++ b/drivers/pci/dwc/pci-layerscape.c
> > @@ -107,33 +107,6 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci)
> > return 1;
> > }
> >
> > -static void ls1021_pcie_host_init(struct pcie_port *pp)
> > -{
> > - struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > - struct ls_pcie *pcie = to_ls_pcie(pci);
> > - struct device *dev = pci->dev;
> > - u32 index[2];
> > -
> > - pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
> > - "fsl,pcie-scfg");
> > - if (IS_ERR(pcie->scfg)) {
> > - dev_err(dev, "No syscfg phandle specified\n");
> > - pcie->scfg = NULL;
> > - return;
> > - }
> > -
> > - if (of_property_read_u32_array(dev->of_node,
> > - "fsl,pcie-scfg", index, 2)) {
> > - pcie->scfg = NULL;
> > - return;
> > - }
> > - pcie->index = index[1];
> > -
> > - dw_pcie_setup_rc(pp);
> > -
> > - ls_pcie_drop_msg_tlp(pcie);
> > -}
> > -
> > static int ls_pcie_link_up(struct dw_pcie *pci)
> > {
> > struct ls_pcie *pcie = to_ls_pcie(pci);
> > @@ -160,6 +133,33 @@ static void ls_pcie_host_init(struct pcie_port *pp)
> > dw_pcie_dbi_ro_wr_dis(pci);
> >
> > ls_pcie_drop_msg_tlp(pcie);
> > +
> > + dw_pcie_setup_rc(pp);
> > +}
> > +
> > +static void ls1021_pcie_host_init(struct pcie_port *pp)
> > +{
> > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > + struct ls_pcie *pcie = to_ls_pcie(pci);
> > + struct device *dev = pci->dev;
> > + u32 index[2];
> > +
> > + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
> > + "fsl,pcie-scfg");
> > + if (IS_ERR(pcie->scfg)) {
> > + dev_err(dev, "No syscfg phandle specified\n");
> > + pcie->scfg = NULL;
> > + return;
> > + }
> > +
> > + if (of_property_read_u32_array(dev->of_node,
> > + "fsl,pcie-scfg", index, 2)) {
> > + pcie->scfg = NULL;
> > + return;
> > + }
> > + pcie->index = index[1];
> > +
> > + ls_pcie_host_init(pp);
>
> The changelog suggests that this is a simple refactoring that doesn't
> fix anything.
>
> But because ls1021_pcie_host_init() now calls ls_pcie_host_init(), it
> now calls:
>
> dw_pcie_dbi_ro_wr_en(pci);
> ls_pcie_fix_class(pcie);
> ls_pcie_clear_multifunction(pcie);
> dw_pcie_dbi_ro_wr_dis(pci);
>
> when it did not call them before.
>
> It's fine with me if you want to do that, but it should be mentioned
> in the changelog.
The order of this series is screwed up, which makes it hard to follow.
5192ec7b24dd ("PCI: layerscape: Add support for LS1043a and LS2080a")
added ls_pcie_host_init(), which didn't call dw_pcie_setup_rc(). I
think that was a bug, and you should fix that first.
Then:
- Rebase on pci/host-designware because it conflicts with patches
I've already applied
(https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git/log/?h=pci/host-designware)
- Make ls_pcie_host_init() call dw_pcie_setup_rc() (fixes
5192ec7b24dd)
- Refactor ls1021_pcie_host_init() to make it call
ls_pcie_host_init() (this will now be no functional change)
- Disable outbound ATUs in ls_pcie_host_init() (bugfix for all
layerscape devices)
- Add DBI write permission accessors and use them in layerscape.
This will make it obvious that PCIE_MISC_CONTROL_1_OFF is moving
from layerscape to designware and that we're actually using these
new interfaces (this will be no functional change).
- Enable write permission in dw_pcie_setup_rc() and remove class
code update from ls_pcie_host_init() This will make it obvious
that fixing dw_pcie_setup_rc() makes ls_pcie_fix_class() obsolete.
Does this dw_pcie_setup_rc() fix mean we can also get rid of the
device class check in qcom_pcie_rd_own_conf()?
I suspect it also means we can drop the write enable in
artpec6_pcie_establish_link().
> > }
> >
> > static int ls_pcie_msi_host_init(struct pcie_port *pp,
> > --
> > 2.1.0.27.g96db324
> >
^ permalink raw reply [flat|nested] 21+ messages in thread* RE: [PATCHv2 4/6] PCI: layerscape: refactor the host_init function
2017-08-14 22:26 ` Bjorn Helgaas
@ 2017-08-15 3:21 ` Z.q. Hou
2017-08-15 9:34 ` Stanimir Varbanov
1 sibling, 0 replies; 21+ messages in thread
From: Z.q. Hou @ 2017-08-15 3:21 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci@vger.kernel.org, bhelgaas@google.com,
jingoohan1@gmail.com, Joao.Pinto@synopsys.com, M.h. Lian,
Mingkai Hu, Roy Zang, Stanimir Varbanov, Niklas Cassel,
Jesper Nilsson
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCHv2 4/6] PCI: layerscape: refactor the host_init function
2017-08-14 22:26 ` Bjorn Helgaas
2017-08-15 3:21 ` Z.q. Hou
@ 2017-08-15 9:34 ` Stanimir Varbanov
2017-08-16 5:19 ` Z.q. Hou
1 sibling, 1 reply; 21+ messages in thread
From: Stanimir Varbanov @ 2017-08-15 9:34 UTC (permalink / raw)
To: Bjorn Helgaas, Zhiqiang Hou
Cc: linux-pci, bhelgaas, jingoohan1, Joao.Pinto, minghuan.lian,
mingkai.hu, roy.zang, Niklas Cassel, Jesper Nilsson
Hi Bjorn,
On 08/15/2017 01:26 AM, Bjorn Helgaas wrote:
> [+cc Stanimir, Niklas, Jesper]
>
> On Mon, Aug 14, 2017 at 04:38:24PM -0500, Bjorn Helgaas wrote:
>> On Thu, Aug 03, 2017 at 04:23:38PM +0800, Zhiqiang Hou wrote:
>>> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>>>
>>> Make the ls1021a's host_init reuse layerscape platform's common
>>> host_init function.
>>>
>>> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>>> ---
>>> V2:
>>> - Removed the disable outbound windows code and the remove duplicate class code
>>> fixup code from this patch.
>>>
>>> drivers/pci/dwc/pci-layerscape.c | 54 ++++++++++++++++++++--------------------
>>> 1 file changed, 27 insertions(+), 27 deletions(-)
>>>
>>> diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
>>> index 09056a6..3533a8c 100644
>>> --- a/drivers/pci/dwc/pci-layerscape.c
>>> +++ b/drivers/pci/dwc/pci-layerscape.c
>>> @@ -107,33 +107,6 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci)
>>> return 1;
>>> }
>>>
<cut>
>
> - Enable write permission in dw_pcie_setup_rc() and remove class
> code update from ls_pcie_host_init() This will make it obvious
> that fixing dw_pcie_setup_rc() makes ls_pcie_fix_class() obsolete.
>
> Does this dw_pcie_setup_rc() fix mean we can also get rid of the
> device class check in qcom_pcie_rd_own_conf()?
Thanks for the CC, I'll manage to test those patches and after that I'll
confirm does this fixes device_class register value for qcom driver.
regards,
Stan
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [PATCHv2 4/6] PCI: layerscape: refactor the host_init function
2017-08-15 9:34 ` Stanimir Varbanov
@ 2017-08-16 5:19 ` Z.q. Hou
0 siblings, 0 replies; 21+ messages in thread
From: Z.q. Hou @ 2017-08-16 5:19 UTC (permalink / raw)
To: Stanimir Varbanov, Bjorn Helgaas
Cc: linux-pci@vger.kernel.org, bhelgaas@google.com,
jingoohan1@gmail.com, Joao.Pinto@synopsys.com, M.h. Lian,
Mingkai Hu, Roy Zang, Niklas Cassel, Jesper Nilsson
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VGhhbmtzLA0KWmhpcWlhbmcNCg==
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [PATCHv2 4/6] PCI: layerscape: refactor the host_init function
2017-08-14 21:38 ` Bjorn Helgaas
2017-08-14 22:26 ` Bjorn Helgaas
@ 2017-08-15 3:05 ` Z.q. Hou
1 sibling, 0 replies; 21+ messages in thread
From: Z.q. Hou @ 2017-08-15 3:05 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci@vger.kernel.org, bhelgaas@google.com,
jingoohan1@gmail.com, Joao.Pinto@synopsys.com, M.h. Lian,
Mingkai Hu, Roy Zang
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MjcuZzk2ZGIzMjQNCj4gPg0KDQpUaGFua3MsDQpaaGlxaWFuZw0K
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCHv2 5/6] PCI: layerscape: Disable the outbound windows configured by bootloader
2017-08-03 8:23 [PATCHv2 0/6] PCI: fix the designware Class code fixup doesn't work issue and refactor ls-pcie host init Zhiqiang Hou
` (3 preceding siblings ...)
2017-08-03 8:23 ` [PATCHv2 4/6] PCI: layerscape: refactor the host_init function Zhiqiang Hou
@ 2017-08-03 8:23 ` Zhiqiang Hou
2017-08-03 8:23 ` [PATCHv2 6/6] PCI: layerscape: remove the duplicate Class field fix code Zhiqiang Hou
5 siblings, 0 replies; 21+ messages in thread
From: Zhiqiang Hou @ 2017-08-03 8:23 UTC (permalink / raw)
To: linux-pci, bhelgaas, jingoohan1, Joao.Pinto
Cc: minghuan.lian, mingkai.hu, roy.zang, Hou Zhiqiang
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Disable the outbound windows configured by bootloader to avoid
one transaction hitting multiple outbound windows because the
function dw_pcie_setup_rc will re-configure the outbound windows
which maybe confict with the bootloader configured.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- New patch split from patch v1 3/3.
drivers/pci/dwc/pci-layerscape.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 3533a8c..ad68894 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -34,6 +34,8 @@
/* PEX Internal Configuration Registers */
#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
+#define PCIE_IATU_NUM 6
+
struct ls_pcie_drvdata {
u32 lut_offset;
u32 ltssm_shift;
@@ -90,6 +92,14 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
}
+static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
+{
+ int i;
+
+ for (i = 0; i < PCIE_IATU_NUM; i++)
+ dw_pcie_disable_atu(pcie->pci, DW_PCIE_REGION_OUTBOUND, i);
+}
+
static int ls1021_pcie_link_up(struct dw_pcie *pci)
{
u32 state;
@@ -127,6 +137,13 @@ static void ls_pcie_host_init(struct pcie_port *pp)
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct ls_pcie *pcie = to_ls_pcie(pci);
+ /*
+ * Disable the outbound windows configured by bootloader to avoid
+ * one transaction hitting multiple outbound windows and the function
+ * dw_pcie_setup_rc will re-configure the outbound windows.
+ */
+ ls_pcie_disable_outbound_atus(pcie);
+
dw_pcie_dbi_ro_wr_en(pci);
ls_pcie_fix_class(pcie);
ls_pcie_clear_multifunction(pcie);
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCHv2 6/6] PCI: layerscape: remove the duplicate Class field fix code
2017-08-03 8:23 [PATCHv2 0/6] PCI: fix the designware Class code fixup doesn't work issue and refactor ls-pcie host init Zhiqiang Hou
` (4 preceding siblings ...)
2017-08-03 8:23 ` [PATCHv2 5/6] PCI: layerscape: Disable the outbound windows configured by bootloader Zhiqiang Hou
@ 2017-08-03 8:23 ` Zhiqiang Hou
5 siblings, 0 replies; 21+ messages in thread
From: Zhiqiang Hou @ 2017-08-03 8:23 UTC (permalink / raw)
To: linux-pci, bhelgaas, jingoohan1, Joao.Pinto
Cc: minghuan.lian, mingkai.hu, roy.zang, Hou Zhiqiang
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The Class Code will be fixed by function dw_pcie_setup_rc.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- New patch split from patch v1 3/3.
drivers/pci/dwc/pci-layerscape.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index ad68894..bf52825 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -73,14 +73,6 @@ static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
}
-/* Fix class value */
-static void ls_pcie_fix_class(struct ls_pcie *pcie)
-{
- struct dw_pcie *pci = pcie->pci;
-
- iowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
-}
-
/* Drop MSG TLP except for Vendor MSG */
static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
{
@@ -145,7 +137,6 @@ static void ls_pcie_host_init(struct pcie_port *pp)
ls_pcie_disable_outbound_atus(pcie);
dw_pcie_dbi_ro_wr_en(pci);
- ls_pcie_fix_class(pcie);
ls_pcie_clear_multifunction(pcie);
dw_pcie_dbi_ro_wr_dis(pci);
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 21+ messages in thread