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[75.72.117.212]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-431f67eb4b3sm47212635ab.12.2025.10.28.13.49.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Oct 2025 13:49:57 -0700 (PDT) Message-ID: Date: Tue, 28 Oct 2025 15:49:54 -0500 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/7] Introduce SpacemiT K1 PCIe phy and host controller To: Johannes Erdfelt Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, vkoul@kernel.org, kishon@kernel.org, dlan@gentoo.org, guodong@riscstar.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, p.zabel@pengutronix.de, christian.bruel@foss.st.com, shradha.t@samsung.com, krishna.chundru@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, namcao@linutronix.de, thippeswamy.havalige@amd.com, inochiama@gmail.com, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20251013153526.2276556-1-elder@riscstar.com> <92ee253f-bf6a-481a-acc2-daf26d268395@riscstar.com> <20251028184250.GM15521@sventech.com> <82848c80-15e0-4c0e-a3f6-821a7f4778a5@riscstar.com> <20251028204832.GN15521@sventech.com> Content-Language: en-US From: Alex Elder In-Reply-To: <20251028204832.GN15521@sventech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 10/28/25 3:48 PM, Johannes Erdfelt wrote: > On Tue, Oct 28, 2025, Alex Elder wrote: >> On 10/28/25 1:42 PM, Johannes Erdfelt wrote: >>> I have been testing this patchset recently as well, but on an Orange Pi >>> RV2 board instead (and an extra RV2 specific patch to enable power to >>> the M.2 slot). >>> >>> I ran into the same symptoms you had ("QID 0 timeout" after about 60 >>> seconds). However, I'm using an Intel 600p. I can confirm my NVME drive >>> seems to work fine with the "pcie_aspm=off" workaround as well. >> >> I don't see this problem, and haven't tried to reproduce it yet. >> >> Mani told me I needed to add these lines to ensure the "runtime >> PM hierarchy of PCIe chain" won't be "broken": >> >> pm_runtime_set_active() >> pm_runtime_no_callbacks() >> devm_pm_runtime_enable() >> >> Just out of curiosity, could you try with those lines added >> just before these assignments in k1_pcie_probe()? >> >> k1->pci.dev = dev; >> k1->pci.ops = &k1_pcie_ops; >> dw_pcie_cap_set(&k1->pci, REQ_RES); >> >> I doubt it will fix what you're seeing, but at the moment I'm >> working on something else. > > Unfortunately there is no difference with the runtime PM hierarchy > additions. > > JE Thank you very much for testing. I'll try to learn more about this in the next day or so and will resolve it if possible before I send the next version of this code. -Alex