From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2EF81885B4; Wed, 23 Apr 2025 13:43:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745415809; cv=none; b=nyPwXqFEr3f0sm6bPjds/aXvoi65UjqjBjzCup+yHV9GZcTnGRFc2YnjIxo0c1BaNRQ4IjUB8tffbxPEXGxqV8cI8TU0gw5T1Z9sYV1PEk7OEuZ1U2ofcmIO3dJzQ4fPmdmMopUMrAMIIXRHeTYK7xbUTmxKrsMr9CBqppjvdMc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745415809; c=relaxed/simple; bh=RkSxu8+Z8qu5S8q9vP5yPS9GfAqR33hG2mgDplUda0A=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=uMhwsyq9gXFANgaff302hEy9iyL3ELkmvrI6mSIXsDLCJSs5aQt2TkySHr1PFn1C6dhuWczUuMf4dA0m/we+rFrpFicR10jbVuMjkLKYgHPXFoYWSnai1vt2zVbn5tSky676UYc2GiVu0xQyrzuoWD+ePqMTItnBSUx98gfFBfM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=m+XMiSyX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="m+XMiSyX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 995B3C4CEE2; Wed, 23 Apr 2025 13:43:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745415809; bh=RkSxu8+Z8qu5S8q9vP5yPS9GfAqR33hG2mgDplUda0A=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=m+XMiSyXBbgt1xJDQN1CCEw+xs1+/DC9D5DEOaSZ7thsO40MS3cDf0JUu0P21h5sj /7A1Ux1kGPGmL1mlvJwXGhQZTzaBCpVG05AzmUoYTbp4WQPWst6Jzo/B2BmURUtxNk mI4/kiZFbe8KiJUMUq2VedOH7saGlOqMwouOBbG/f14i/eoI+0H/gZmumGktjQ0exd SFcaA4V9XAD5XvZR7bbw3RL5m2FWvTCB/OdS5zg5F4R0fHwKVxCY7aq1t2FXESldjO fbVvzi+GNTAc4v6NDZTmTv3C6ibPBxtzuiHovfSOhdjCWT8Kcd6AkNQjqUnZ/2Z2BO E1KeXoxXkCjew== Date: Wed, 23 Apr 2025 15:43:24 +0200 From: Niklas Cassel To: Hans Zhang <18255117159@163.com> Cc: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, heiko@sntech.de, manivannan.sadhasivam@linaro.org, robh@kernel.org, jingoohan1@gmail.com, shawn.lin@rock-chips.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: Re: [PATCH v2 2/3] PCI: dw-rockchip: Reorganize register and bitfield definitions Message-ID: References: <20250423105415.305556-1-18255117159@163.com> <20250423105415.305556-3-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250423105415.305556-3-18255117159@163.com> On Wed, Apr 23, 2025 at 06:54:14PM +0800, Hans Zhang wrote: > Register definitions were scattered with ambiguous names (e.g., > PCIE_RDLH_LINK_UP_CHGED in PCIE_CLIENT_INTR_STATUS_MISC) and lacked > hierarchical grouping. Magic values for bit operations reduced code > clarity. > > Group registers and their associated bitfields logically. This improves > maintainability and aligns the code with hardware documentation. > > Signed-off-by: Hans Zhang <18255117159@163.com> > --- > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 71 ++++++++++++------- > 1 file changed, 45 insertions(+), 26 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > index fd5827bbfae3..6cf75160fb1c 100644 > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > @@ -34,30 +34,49 @@ > > #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) > > -#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) > -#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) > -#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) > -#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) > -#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04 > -#define PCIE_CLIENT_INTR_STATUS_MISC 0x10 > -#define PCIE_CLIENT_INTR_MASK_MISC 0x24 > -#define PCIE_CLIENT_POWER 0x2c > -#define PCIE_CLIENT_MSG_GEN 0x34 > -#define PME_READY_ENTER_L23 BIT(3) > -#define PME_TURN_OFF (BIT(4) | BIT(20)) > -#define PME_TO_ACK (BIT(9) | BIT(25)) > -#define PCIE_SMLH_LINKUP BIT(16) > -#define PCIE_RDLH_LINKUP BIT(17) > -#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) > -#define PCIE_RDLH_LINK_UP_CHGED BIT(1) > -#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) > -#define PCIE_CLIENT_GENERAL_CONTROL 0x0 > +/* General Control Register */ > +#define PCIE_CLIENT_GENERAL_CON 0x0 > +#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) > +#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) > +#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) > +#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) > + > +/* Interrupt Status Register Related to Message Reception */ > +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x4 > + > +/* Interrupt Status Register Related to Legacy Interrupt */ > #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 > + > +/* Interrupt Status Register Related to Miscellaneous Operation */ double spaces, other comments just have one space. > +#define PCIE_CLIENT_INTR_STATUS_MISC 0x10 > +#define PCIE_RDLH_LINK_UP_CHGED BIT(1) > +#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) > + > +/* Interrupt Mask Register Related to Legacy Interrupt */ > #define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c > + > +/* Interrupt Mask Register Related to Miscellaneous Operation */ > +#define PCIE_CLIENT_INTR_MASK_MISC 0x24 > + > +/* Power Management Control Register */ > +#define PCIE_CLIENT_POWER_CON 0x2c > +#define PME_READY_ENTER_L23 BIT(3) > + > +/* Message Generation Control Register */ double spaces, other comments just have one space. > +#define PCIE_CLIENT_MSG_GEN_CON 0x34 > +#define PME_TURN_OFF HIWORD_UPDATE_BIT(BIT(4)) > +#define PME_TO_ACK HIWORD_UPDATE_BIT(BIT(9)) > + > +/* Hot Reset Control Register */ > #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 > +#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) > + > +/* LTSSM Status Register */ > #define PCIE_CLIENT_LTSSM_STATUS 0x300 > -#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) > -#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) > +#define PCIE_SMLH_LINKUP BIT(16) > +#define PCIE_RDLH_LINKUP BIT(17) > +#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) > +#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) > > struct rockchip_pcie { > struct dw_pcie pci; > @@ -176,13 +195,13 @@ static u32 rockchip_pcie_get_pure_ltssm(struct dw_pcie *pci) > static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) > { > rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, > - PCIE_CLIENT_GENERAL_CONTROL); > + PCIE_CLIENT_GENERAL_CON); > } > > static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip) > { > rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM, > - PCIE_CLIENT_GENERAL_CONTROL); > + PCIE_CLIENT_GENERAL_CON); > } > > static int rockchip_pcie_link_up(struct dw_pcie *pci) > @@ -274,8 +293,8 @@ static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp) > u32 status; > > /* 1. Broadcast PME_Turn_Off Message, bit 4 self-clear once done */ > - rockchip_pcie_writel_apb(rockchip, PME_TURN_OFF, PCIE_CLIENT_MSG_GEN); > - ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_MSG_GEN, > + rockchip_pcie_writel_apb(rockchip, PME_TURN_OFF, PCIE_CLIENT_MSG_GEN_CON); > + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_MSG_GEN_CON, > status, !(status & BIT(4)), PCIE_PME_TO_L2_TIMEOUT_US / 10, > PCIE_PME_TO_L2_TIMEOUT_US); > if (ret) { > @@ -294,7 +313,7 @@ static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp) > > /* 3. Clear PME_TO_Ack and Wait for ready to enter L23 message */ > rockchip_pcie_writel_apb(rockchip, PME_TO_ACK, PCIE_CLIENT_INTR_STATUS_MSG_RX); > - ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_POWER, > + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_POWER_CON, > status, status & PME_READY_ENTER_L23, > PCIE_PME_TO_L2_TIMEOUT_US / 10, > PCIE_PME_TO_L2_TIMEOUT_US); > @@ -552,7 +571,7 @@ static void rockchip_pcie_ltssm_enable_control_mode(struct rockchip_pcie *rockch > val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); > rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); > > - rockchip_pcie_writel_apb(rockchip, mode, PCIE_CLIENT_GENERAL_CONTROL); > + rockchip_pcie_writel_apb(rockchip, mode, PCIE_CLIENT_GENERAL_CON); I can see why you renamed PCIE_CLIENT_GENERAL_CONTROL to PCIE_CLIENT_GENERAL_CON (to match PCIE_CLIENT_MSG_GEN_CON). But now we have PCIE_CLIENT_MSG_GEN_CON / PCIE_CLIENT_GENERAL_CON and PCIE_CLIENT_HOT_RESET_CTRL. _CTRL seems like a more common shortening. How about renaming all three to end with _CTRL ?