From: Niklas Cassel <cassel@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Wilfred Mallawa" <wilfred.mallawa@wdc.com>,
"Damien Le Moal" <dlemoal@kernel.org>,
"Hans Zhang" <18255117159@163.com>,
"Laszlo Fiat" <laszlo.fiat@proton.me>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v2 1/4] PCI: dw-rockchip: Do not enumerate bus before endpoint devices are ready
Date: Wed, 4 Jun 2025 13:40:52 +0200 [thread overview]
Message-ID: <aEAwxFysCgdJCD54@ryzen> (raw)
In-Reply-To: <20250603181250.GA473171@bhelgaas>
On Tue, Jun 03, 2025 at 01:12:50PM -0500, Bjorn Helgaas wrote:
>
> Hmmm, sorry, I misinterpreted both 1/4 and 2/4. I read them as "add
> this delay so the PLEXTOR device works", but in fact, I think in both
> cases, the delay is actually to enforce the PCIe r6.0, sec 6.6.1,
> requirement for software to wait 100ms before issuing a config
> request, and the fact that it makes PLEXTOR work is a side effect of
> that.
Well, the Plextor NVMe drive used to work with previous kernels,
but regressed.
But yes, the delay was added to enforce "PCIe r6.0, sec 6.6.1"
requirement for software to wait 100ms, which once again makes
the Plextor NVMe drive work.
>
> The beginning of that 100ms delay is "exit from Conventional Reset"
> (ports that support <= 5.0 GT/s) or "link training completes" (ports
> that support > 5.0 GT/s).
>
> I think we lack that 100ms delay in dwc drivers in general. The only
> generic dwc delay is in dw_pcie_host_init() via the LINK_WAIT_SLEEP_MS
> in dw_pcie_wait_for_link(), but that doesn't count because it's
> *before* the link comes up. We have to wait 100ms *after* exiting
> Conventional Reset or completing link training.
In dw_pcie_wait_for_link(), in the first iteration of the loop, the link
will never be up (because the link was just started),
dw_pcie_wait_for_link() will then sleep for LINK_WAIT_SLEEP_MS (90 ms),
before trying again.
Most likely the link training took way less than 100 ms, so most of those
90 ms will probably be after link training has completed.
That is most likely why Plextor worked on older kernels (which does not
use the link up IRQ).
If we add a 100 ms sleep after wait_for_link(), then I suggest that we
also reduce LINK_WAIT_SLEEP_MS to something shorter.
>
> We don't know when the exit from Conventional Reset was, but it was
> certainly before the link came up. In the absence of a timestamp for
> exit from reset, starting the wait after link-up is probably the best
> we can do. This could be either after dw_pcie_wait_for_link() finds
> the link up or when we handle the link-up interrupt.
>
> Patches 1 and 2 would fix the link-up interrupt case. I think we need
> another patch for the dwc core for dw_pcie_wait_for_link().
I agree, sounds like a plan.
>
> I wish I'd had time to spend on this and include patches 1 and 2, but
> we're up against the merge window wire and I'll be out the end of this
> week, so I think they'll have to wait. It seems like something we can
> still justify for v6.16 though.
I think it sounds good to target this as fixes for v6.16.
Do you plan to send out something after -rc1, or do you prefer me to do it?
Kind regards,
Niklas
next prev parent reply other threads:[~2025-06-04 11:40 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-06 7:39 [PATCH v2 0/4] PCI: dwc: Link Up IRQ fixes Niklas Cassel
2025-05-06 7:39 ` [PATCH v2 1/4] PCI: dw-rockchip: Do not enumerate bus before endpoint devices are ready Niklas Cassel
2025-05-06 11:32 ` Laszlo Fiat
2025-05-06 22:23 ` Wilfred Mallawa
2025-05-28 22:42 ` Bjorn Helgaas
2025-05-30 13:57 ` Niklas Cassel
2025-05-30 15:21 ` Bjorn Helgaas
2025-05-30 15:59 ` Manivannan Sadhasivam
2025-05-30 17:19 ` Bjorn Helgaas
2025-05-30 17:24 ` Niklas Cassel
2025-05-30 19:43 ` Bjorn Helgaas
2025-05-31 6:47 ` Manivannan Sadhasivam
2025-06-03 14:08 ` Niklas Cassel
2025-06-03 18:12 ` Bjorn Helgaas
2025-06-04 11:40 ` Niklas Cassel [this message]
2025-06-04 17:10 ` Manivannan Sadhasivam
2025-06-04 18:44 ` Bjorn Helgaas
2025-06-05 12:28 ` Niklas Cassel
2025-06-05 13:22 ` Manivannan Sadhasivam
2025-06-05 19:27 ` Bjorn Helgaas
2025-05-06 7:39 ` [PATCH v2 2/4] PCI: qcom: " Niklas Cassel
2025-05-06 10:11 ` Krishna Chaitanya Chundru
2025-05-06 11:29 ` Laszlo Fiat
2025-05-06 22:24 ` Wilfred Mallawa
2025-05-06 7:39 ` [PATCH v2 3/4] PCI: dw-rockchip: Replace PERST sleep time with proper macro Niklas Cassel
2025-05-06 9:07 ` Hans Zhang
2025-05-06 11:36 ` Laszlo Fiat
2025-05-06 22:24 ` Wilfred Mallawa
2025-05-06 7:39 ` [PATCH v2 4/4] PCI: qcom: " Niklas Cassel
2025-05-06 9:07 ` Hans Zhang
2025-05-06 10:12 ` Krishna Chaitanya Chundru
2025-05-06 11:37 ` Laszlo Fiat
2025-05-06 22:25 ` Wilfred Mallawa
2025-05-06 14:33 ` [PATCH v2 0/4] PCI: dwc: Link Up IRQ fixes Niklas Cassel
2025-05-06 14:51 ` Laszlo Fiat
2025-05-13 10:53 ` Manivannan Sadhasivam
2025-05-13 14:07 ` Niklas Cassel
2025-05-15 17:33 ` Laszlo Fiat
2025-05-16 10:00 ` Niklas Cassel
2025-05-16 18:48 ` Laszlo Fiat
2025-05-19 9:44 ` Niklas Cassel
2025-05-19 12:10 ` Manivannan Sadhasivam
2025-05-19 12:37 ` Manivannan Sadhasivam
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