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Tue, 10 Jun 2025 20:46:10 -0700 (PDT) Received: from geday ([2804:7f2:800b:5ecc::dead:c001]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-87eeae8551dsm2251922241.14.2025.06.10.20.46.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 20:46:09 -0700 (PDT) Date: Wed, 11 Jun 2025 00:46:03 -0300 From: Geraldo Nascimento To: Bjorn Helgaas Cc: linux-rockchip@lists.infradead.org, Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 1/4] PCI: pcie-rockchip: add bits for Target Link Speed in LCS_2 Message-ID: References: <20250610200744.GA820589@bhelgaas> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250610200744.GA820589@bhelgaas> On Tue, Jun 10, 2025 at 03:07:44PM -0500, Bjorn Helgaas wrote: > On Sat, Jun 07, 2025 at 08:00:54AM -0300, Geraldo Nascimento wrote: > This stuff: > > #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) > #define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) > #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) > #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) > #define PCIE_RC_CONFIG_LCS_2 (PCIE_RC_CONFIG_BASE + 0xf0) > > *Looks* like it might be duplicates of: > > #define PCI_EXP_DEVCAP 0x04 /* Device capabilities */ > #define PCI_EXP_DEVCTL 0x08 /* Device Control */ > #define PCI_EXP_LNKCAP 0x0c /* Link Capabilities */ Hi again Bjorn, Your message reminded me of something that may be important. During my debugging I had the mild impression L0s capability is not being cleared from Link Capabilities Register in the presence of "aspm-no-l0s" DT property. I can't confirm it right now but I might revisit this later on. From what I've seen it can only be cleared from inside the port init in pcie-rockchip.c and does nothing in present form. Not a clear, confirmable report but something to watch out for... Regards, Geraldo Nascimento