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From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linux-rockchip@lists.infradead.org,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH v2 1/4] PCI: pcie-rockchip: add Link Control and Status Register 2
Date: Thu, 12 Jun 2025 17:49:57 -0300	[thread overview]
Message-ID: <aEs9daeceXkePg7y@geday> (raw)
In-Reply-To: <20250611194259.GA825364@bhelgaas>

On Wed, Jun 11, 2025 at 02:42:59PM -0500, Bjorn Helgaas wrote:
> I would do a pure conversion patch of the existing #defines.  Then I
> suspect you wouldn't need a patch to add the Link 2 registers at all
> because you could just use the #defines from pci_regs.h.

Hi Bjorn,

I've hit roadblock, maybe you can help?

PCIE_RC_CONFIG_DCR_CSPL_LIMIT is defined as 0xff...

I'd like to kill that define too, since it will be
orphaned.

But hardcoding 0xff seems like illegible solution.

Perhaps there is another standard define that
maps to 0xff that I can use? Anyone comes
to your mind?

Thanks!
Geraldo Nascimento

  parent reply	other threads:[~2025-06-12 20:50 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-10 21:19 [RFC PATCH v2 0/4] Quality Improvements for Rockchip-IP PCIe Geraldo Nascimento
2025-06-10 21:19 ` [RFC PATCH v2 1/4] PCI: pcie-rockchip: add Link Control and Status Register 2 Geraldo Nascimento
2025-06-11 19:42   ` Bjorn Helgaas
2025-06-12  0:48     ` Geraldo Nascimento
2025-06-12 20:49     ` Geraldo Nascimento [this message]
2025-06-12 21:26       ` Bjorn Helgaas
2025-06-10 21:20 ` [RFC PATCH v2 2/4] PCI: rockchip-host: Set Target Link Speed before retraining Geraldo Nascimento
2025-06-10 21:20 ` [RFC PATCH v2 3/4] phy: rockchip-pcie: enable all four lanes Geraldo Nascimento
2025-06-10 21:25 ` [RFC PATCH v2 4/4] phy: rockchip-pcie: adjust read mask and write strobe disable Geraldo Nascimento

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