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Fri, 13 Jun 2025 13:32:59 -0700 (PDT) Received: from geday ([2804:7f2:800b:84a2::dead:c001]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-313c1c5fd7esm3812515a91.37.2025.06.13.13.32.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jun 2025 13:32:58 -0700 (PDT) Date: Fri, 13 Jun 2025 17:32:52 -0300 From: Geraldo Nascimento To: Bjorn Helgaas Cc: linux-rockchip@lists.infradead.org, Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RESEND RFC PATCH v4 5/5] phy: rockchip-pcie: Adjust read mask and write Message-ID: References: <20250613202056.GA974155@bhelgaas> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250613202056.GA974155@bhelgaas> On Fri, Jun 13, 2025 at 03:20:56PM -0500, Bjorn Helgaas wrote: > On Fri, Jun 13, 2025 at 12:06:28PM -0300, Geraldo Nascimento wrote: > > Section 17.6.10 of the RK3399 TRM "PCIe PIPE PHY registers Description" > > defines asynchronous strobe TEST_WRITE which should be enabled then > > disabled and seems to have been copy-pasted as of current. Adjust it. > > While at it, adjust read mask which should be the same as write mask. > > Not a PCI patch, but "adjust" doesn't tell us what's happening. > > From reading the patch, I assume that since PHY_CFG_WR_ENABLE and > PHY_CFG_WR_DISABLE were both defined to be 1, this code: > > regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf, > HIWORD_UPDATE(PHY_CFG_WR_DISABLE, > PHY_CFG_WR_MASK, > PHY_CFG_WR_SHIFT)); > > actually left something *enabled* when it meant to disable it. > > Maybe the subject/commit log could say something about actually > disabling whatever this is instead of leaving it enabled? > > PHY_CFG_RD_MASK appears unused, so maybe it should be just removed. Your line of reasoning is correct regarding the TEST_WRITE async strobe register, and there's a picture of the flow in Section 17.5.3 (PCIe PHY Configuration) of the RK3399 TRM, Part 2. I'll make sure to be more clear in the commit message. Regarding PHY_CFG_RD_MASK, yes, it is unused AFAICT and can be removed. It's leftover from BSP where the debugging function phy_rd_cfg exists. Thanks, Geraldo Nascimento