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Fri, 20 Jun 2025 08:23:50 -0700 (PDT) Received: from geday ([2804:7f2:800b:cd3b::dead:c001]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3159e07d027sm1904055a91.43.2025.06.20.08.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jun 2025 08:23:49 -0700 (PDT) Date: Fri, 20 Jun 2025 12:23:42 -0300 From: Geraldo Nascimento To: Robin Murphy Cc: linux-rockchip@lists.infradead.org, Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Rick wertenbroek , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v5 4/4] phy: rockchip-pcie: Adjust read mask and write Message-ID: References: <7068a941037eca8ef37cc65e8e08a136c7aac924.1749833987.git.geraldogabriel@gmail.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, Jun 20, 2025 at 03:19:06PM +0100, Robin Murphy wrote: > On 2025-06-13 6:04 pm, Geraldo Nascimento wrote: > > Section 17.6.10 of the RK3399 TRM "PCIe PIPE PHY registers Description" > > defines asynchronous strobe TEST_WRITE which should be enabled then > > disabled and seems to have been copy-pasted as of current. Adjust it. > > FWIW that's a bit hard to make sense of, given that it bears no relation > whatsoever to the naming used in the code :/ > > (Not least because the mapping of register fields to phy signals here is > really a property of GRF_SOC_CON8 rather than the phy itself) Hi Robin, will adjust for a better commit message, thank you. > > > While at it, adjust read mask which should be the same as write mask. > > Which write mask? Certainly not PHY_CFG_WR_MASK... However as this > definition is unused since 64cdc0360811 ("phy: rockchip-pcie: remove > unused phy_rd_cfg function"), I don't see much point in touching it > other than to remove it entirely. If it is the case that only the > address field is significant for whatever a "read" operation actually > means, well then that's just another job for ADDR_MASK (which I guess is > what the open-coded business with PHY_CFG_PLL_LOCK is actually doing...) Oh, I already had agreed on Bjorn's suggestion to drop PHY_CFG_RD_MASK for good from code, but I appreciate your input too. Thanks, Geraldo Nascimento > > Thanks, > Robin. > > > Signed-off-by: Geraldo Nascimento > > --- > > drivers/phy/rockchip/phy-rockchip-pcie.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c > > index 48bcc7d2b33b..35d2523ee776 100644 > > --- a/drivers/phy/rockchip/phy-rockchip-pcie.c > > +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c > > @@ -30,9 +30,9 @@ > > #define PHY_CFG_ADDR_SHIFT 1 > > #define PHY_CFG_DATA_MASK 0xf > > #define PHY_CFG_ADDR_MASK 0x3f > > -#define PHY_CFG_RD_MASK 0x3ff > > +#define PHY_CFG_RD_MASK 0x3f > > #define PHY_CFG_WR_ENABLE 1 > > -#define PHY_CFG_WR_DISABLE 1 > > +#define PHY_CFG_WR_DISABLE 0 > > #define PHY_CFG_WR_SHIFT 0 > > #define PHY_CFG_WR_MASK 1 > > #define PHY_CFG_PLL_LOCK 0x10 >