Re: [RFC PATCH v5 3/4] phy: rockchip-pcie: Enable all four lanes

Robin Murphy
2025-06-20T12:04:50Z

On 2025-06-13 6:03 pm, Geraldo Nascimento wrote:
> Current code enables only Lane 0 because pwr_cnt will be incremented
> on first call to the function. Use for-loop to enable all 4 lanes
> through GRF.

If this was really necessary, then surely it would also need the
equivalent changes in rockchip_pcie_phy_power_off() too?

However, I'm not sure it *is* necessary - the NVMe on my RK3399 board
happily claims to be using an x4 link, so I stuck a print of inst->index
in this function, and sure enough I do see it being called for each
instance already:

[ 1.737479] phy phy-ff770000.syscon:pcie-phy.1: power_on 0
[ 1.738810] phy phy-ff770000.syscon:pcie-phy.2: power_on 1
[ 1.745193] phy phy-ff770000.syscon:pcie-phy.3: power_on 2
[ 1.745196] phy phy-ff770000.syscon:pcie-phy.4: power_on 3

Thanks,
Robin.

> Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
> ---
> drivers/phy/rockchip/phy-rockchip-pcie.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
> index bd44af36c67a..48bcc7d2b33b 100644
> --- a/drivers/phy/rockchip/phy-rockchip-pcie.c
> +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
> @@ -176,11 +176,13 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
> PHY_CFG_ADDR_MASK,
> PHY_CFG_ADDR_SHIFT));
>
> - regmap_write(rk_phy->reg_base,
> - rk_phy->phy_data->pcie_laneoff,
> - HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
> - PHY_LANE_IDLE_MASK,
> - PHY_LANE_IDLE_A_SHIFT + inst->index));
> + for (int i=0; i < PHY_MAX_LANE_NUM; i++) {
> + regmap_write(rk_phy->reg_base,
> + rk_phy->phy_data->pcie_laneoff,
> + HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
> + PHY_LANE_IDLE_MASK,
> + PHY_LANE_IDLE_A_SHIFT + i));
> + }
>
> /*
> * No documented timeout value for phy operation below,