From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: linux-rockchip@lists.infradead.org,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Rick wertenbroek" <rick.wertenbroek@gmail.com>,
linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH v5 3/4] phy: rockchip-pcie: Enable all four lanes
Date: Fri, 20 Jun 2025 10:00:30 -0300 [thread overview]
Message-ID: <aFVbbnl9UscGQoqC@geday> (raw)
In-Reply-To: <413e7ed5-fc4d-4e4e-9cb4-234c41db267b@arm.com>
On Fri, Jun 20, 2025 at 01:47:35PM +0100, Robin Murphy wrote:
> Ah, I put that print at the top of the function - on second look now I
> see that there's an awkward mix of per-lane and global data, and pwr_cnt
> is actually the latter. Sure enough, moving the print past that check I
> only see it once.
Hi Robin, thanks for re-testing and no worries.
>
> However, I still don't think blindly enabling all the lanes is the right
> thing to do either; I'd imagine something like the (untested) diff below
> would be more appropriate. That would then seem to balance with what
> power_off is doing.
Thanks for the suggestion, I'll make sure to test it appropriately
before sending v6.
Thanks!
Geraldo Nascimento
>
> Thanks,
> Robin.
>
> ----->8-----
> diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
> index bd44af36c67a..a34a983db16c 100644
> --- a/drivers/phy/rockchip/phy-rockchip-pcie.c
> +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
> @@ -160,11 +160,8 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
>
> guard(mutex)(&rk_phy->pcie_mutex);
>
> - if (rk_phy->pwr_cnt++) {
> - return 0;
> - }
> -
> - err = reset_control_deassert(rk_phy->phy_rst);
> + if (rk_phy->pwr_cnt++)
> + err = reset_control_deassert(rk_phy->phy_rst);
> if (err) {
> dev_err(&phy->dev, "deassert phy_rst err %d\n", err);
> rk_phy->pwr_cnt--;
> @@ -181,6 +178,8 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
> HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
> PHY_LANE_IDLE_MASK,
> PHY_LANE_IDLE_A_SHIFT + inst->index));
> + if (rk_phy->pwr_cnt)
> + return 0;
>
> /*
> * No documented timeout value for phy operation below,
>
next prev parent reply other threads:[~2025-06-20 13:00 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 17:03 [RFC PATCH v5 0/4] PCI: rockchip: Improve driver quality Geraldo Nascimento
2025-06-13 17:03 ` [RFC PATCH v5 1/4] PCI: rockchip: Use standard PCIe defines Geraldo Nascimento
2025-06-13 17:03 ` [RFC PATCH v5 2/4] PCI: rockchip: Set Target Link Speed before retraining Geraldo Nascimento
2025-06-13 18:06 ` Geraldo Nascimento
2025-06-20 12:33 ` Robin Murphy
2025-06-20 12:43 ` Geraldo Nascimento
2025-06-13 17:03 ` [RFC PATCH v5 3/4] phy: rockchip-pcie: Enable all four lanes Geraldo Nascimento
2025-06-20 12:04 ` Robin Murphy
2025-06-20 12:26 ` Geraldo Nascimento
2025-06-20 12:47 ` Robin Murphy
2025-06-20 13:00 ` Geraldo Nascimento [this message]
2025-06-20 12:50 ` Geraldo Nascimento
2025-06-13 17:04 ` [RFC PATCH v5 4/4] phy: rockchip-pcie: Adjust read mask and write Geraldo Nascimento
2025-06-20 14:19 ` Robin Murphy
2025-06-20 15:23 ` Geraldo Nascimento
2025-06-20 18:35 ` Geraldo Nascimento
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