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Fri, 20 Jun 2025 06:00:37 -0700 (PDT) Received: from geday ([2804:7f2:800b:cab9::dead:c001]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7490a69b973sm1994049b3a.157.2025.06.20.06.00.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jun 2025 06:00:36 -0700 (PDT) Date: Fri, 20 Jun 2025 10:00:30 -0300 From: Geraldo Nascimento To: Robin Murphy Cc: linux-rockchip@lists.infradead.org, Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Rick wertenbroek , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v5 3/4] phy: rockchip-pcie: Enable all four lanes Message-ID: References: <4c2c9a15-50bc-4a89-b5fe-d9014657fca7@arm.com> <413e7ed5-fc4d-4e4e-9cb4-234c41db267b@arm.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <413e7ed5-fc4d-4e4e-9cb4-234c41db267b@arm.com> On Fri, Jun 20, 2025 at 01:47:35PM +0100, Robin Murphy wrote: > Ah, I put that print at the top of the function - on second look now I > see that there's an awkward mix of per-lane and global data, and pwr_cnt > is actually the latter. Sure enough, moving the print past that check I > only see it once. Hi Robin, thanks for re-testing and no worries. > > However, I still don't think blindly enabling all the lanes is the right > thing to do either; I'd imagine something like the (untested) diff below > would be more appropriate. That would then seem to balance with what > power_off is doing. Thanks for the suggestion, I'll make sure to test it appropriately before sending v6. Thanks! Geraldo Nascimento > > Thanks, > Robin. > > ----->8----- > diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c > index bd44af36c67a..a34a983db16c 100644 > --- a/drivers/phy/rockchip/phy-rockchip-pcie.c > +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c > @@ -160,11 +160,8 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) > > guard(mutex)(&rk_phy->pcie_mutex); > > - if (rk_phy->pwr_cnt++) { > - return 0; > - } > - > - err = reset_control_deassert(rk_phy->phy_rst); > + if (rk_phy->pwr_cnt++) > + err = reset_control_deassert(rk_phy->phy_rst); > if (err) { > dev_err(&phy->dev, "deassert phy_rst err %d\n", err); > rk_phy->pwr_cnt--; > @@ -181,6 +178,8 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) > HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, > PHY_LANE_IDLE_MASK, > PHY_LANE_IDLE_A_SHIFT + inst->index)); > + if (rk_phy->pwr_cnt) > + return 0; > > /* > * No documented timeout value for phy operation below, >