From: Niklas Cassel <cassel@kernel.org>
To: "Jingoo Han" <jingoohan1@gmail.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Kevin Xie" <kevin.xie@starfivetech.com>,
"Kever Yang" <kever.yang@rock-chips.com>
Cc: Wilfred Mallawa <wilfred.mallawa@wdc.com>,
Damien Le Moal <dlemoal@kernel.org>,
Laszlo Fiat <laszlo.fiat@proton.me>,
Simon Xue <xxm@rock-chips.com>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org,
linux-arm-msm@vger.kernel.org
Subject: Re: [PATCH v3 0/6] PCI: dwc: Do not enumerate bus before endpoint devices are ready
Date: Mon, 23 Jun 2025 12:12:44 +0200 [thread overview]
Message-ID: <aFkonAnTZN80jsrP@ryzen> (raw)
In-Reply-To: <20250613124839.2197945-8-cassel@kernel.org>
On Fri, Jun 13, 2025 at 02:48:39PM +0200, Niklas Cassel wrote:
> Hello all,
>
> The DWC PCIe controller driver currently does not follow the PCIe
> specification with regards to the delays after link training, before
> sending out configuration requests. This series fixes this.
>
> At the same time, PATCH 1/4 addresses a regression where a Plextor
> NVMe drive fails to be configured correctly. With this series, the
> Plextor NVMe drive works once again.
>
>
> Kind regards,
> Niklas
>
>
> Changes since v2:
> -Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS.
>
>
> Niklas Cassel (6):
> PCI: Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to
> PCIE_RESET_CONFIG_WAIT_MS
> PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS
> PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ
> PCI: qcom: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ
> PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link
> up
> PCI: dwc: Reduce LINK_WAIT_SLEEP_MS
>
> drivers/pci/controller/dwc/pcie-designware.c | 13 ++++++++++++-
> drivers/pci/controller/dwc/pcie-designware.h | 13 +++++++++----
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 +
> drivers/pci/controller/dwc/pcie-qcom.c | 1 +
> drivers/pci/controller/pcie-rockchip-host.c | 2 +-
> drivers/pci/controller/plda/pcie-starfive.c | 2 +-
> drivers/pci/pci.h | 9 +--------
> 7 files changed, 26 insertions(+), 15 deletions(-)
>
> --
> 2.49.0
>
Gentle ping
prev parent reply other threads:[~2025-06-23 10:12 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 12:48 [PATCH v3 0/6] PCI: dwc: Do not enumerate bus before endpoint devices are ready Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 1/6] PCI: Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 2/6] PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS Niklas Cassel
2025-06-23 14:25 ` Manivannan Sadhasivam
2025-06-13 12:48 ` [PATCH v3 3/6] PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 4/6] PCI: qcom: " Niklas Cassel
2025-06-23 14:27 ` Manivannan Sadhasivam
2025-06-25 9:06 ` Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 5/6] PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up Niklas Cassel
2025-06-23 14:28 ` Manivannan Sadhasivam
2025-06-25 9:20 ` Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 6/6] PCI: dwc: Reduce LINK_WAIT_SLEEP_MS Niklas Cassel
2025-06-23 14:52 ` Manivannan Sadhasivam
2025-06-25 9:02 ` Niklas Cassel
2025-06-23 10:12 ` Niklas Cassel [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aFkonAnTZN80jsrP@ryzen \
--to=cassel@kernel.org \
--cc=bhelgaas@google.com \
--cc=dlemoal@kernel.org \
--cc=heiko@sntech.de \
--cc=jingoohan1@gmail.com \
--cc=kever.yang@rock-chips.com \
--cc=kevin.xie@starfivetech.com \
--cc=kwilczynski@kernel.org \
--cc=laszlo.fiat@proton.me \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=mani@kernel.org \
--cc=robh@kernel.org \
--cc=shawn.lin@rock-chips.com \
--cc=wilfred.mallawa@wdc.com \
--cc=xxm@rock-chips.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).