From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: Philipp Stanner <pstanner@redhat.com>
Cc: linux-rockchip@lists.infradead.org,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Rick wertenbroek" <rick.wertenbroek@gmail.com>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Valmantas Paliksa" <walmis@gmail.com>,
linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [RESEND PATCH v9 1/4] PCI: rockchip: Use standard PCIe defines
Date: Tue, 1 Jul 2025 09:03:31 -0300 [thread overview]
Message-ID: <aGPOkw2G2IeNhDRy@geday> (raw)
In-Reply-To: <ce0fdbf2753075056c227ce7567a69386a5aa0a3.camel@redhat.com>
On Tue, Jul 01, 2025 at 09:54:51AM +0200, Philipp Stanner wrote:
> On Mon, 2025-06-30 at 19:24 -0300, Geraldo Nascimento wrote:
> > Current code uses custom-defined register offsets and bitfields for
> > standard PCIe registers. Change to using standard PCIe defines. Since
> > we are now using standard PCIe defines, drop unused custom-defined
> > ones,
> > which are now referenced from offset at added Capabilities Register.
>
> This could be phrased a bit more cleanly. At least I don't get exactly
> what "from offset" means. You mean you replace the unused custom ones?
> But if they're unused, why are they even being replaced?
Hi Philipp!
"from offset" means we use standard PCIe defines for registers that are
adjacent to Capabilities Register, and we reference them from the offset
at Capabilities Register.
No, all registers replaced are in use, unused in that context means they
(the custom-defined registers which can be referenced starting from
Capabilities Register address) become unused after the change, only.
>
>
> >
> > Suggested-By: Bjorn Helgaas <bhelgaas@google.com>
>
> s/By/by
Thanks for the capitalization catch. Unfortunately there's little I can do
now that Mani went ahead and applied the first two patches (directly
related to PCI subsystem).
Thanks,
Geraldo Nascimento
>
>
> P.
next prev parent reply other threads:[~2025-07-01 12:03 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-30 22:24 [RESEND PATCH v9 0/4] PCI: rockchip: Improve driver quality Geraldo Nascimento
2025-06-30 22:24 ` [RESEND PATCH v9 1/4] PCI: rockchip: Use standard PCIe defines Geraldo Nascimento
2025-07-01 7:54 ` Philipp Stanner
2025-07-01 12:03 ` Geraldo Nascimento [this message]
2025-07-01 12:44 ` Manivannan Sadhasivam
2025-07-07 22:22 ` Bjorn Helgaas
2025-07-07 23:04 ` Geraldo Nascimento
2025-06-30 22:24 ` [RESEND PATCH v9 2/4] PCI: rockchip: Set Target Link Speed before retraining Geraldo Nascimento
2025-06-30 22:25 ` [RESEND PATCH v9 3/4] phy: rockchip-pcie: Enable all four lanes if required Geraldo Nascimento
2025-06-30 22:25 ` [RESEND PATCH v9 4/4] phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal Geraldo Nascimento
2025-07-01 7:43 ` (subset) [RESEND PATCH v9 0/4] PCI: rockchip: Improve driver quality Manivannan Sadhasivam
2025-07-22 13:37 ` Vinod Koul
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