linux-pci.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Nicolin Chen <nicolinc@nvidia.com>
To: Ethan Zhao <etzhao1900@gmail.com>
Cc: <robin.murphy@arm.com>, <joro@8bytes.org>, <bhelgaas@google.com>,
	<jgg@nvidia.com>, <will@kernel.org>,
	<robin.clark@oss.qualcomm.com>, <yong.wu@mediatek.com>,
	<matthias.bgg@gmail.com>,
	<angelogioacchino.delregno@collabora.com>,
	<thierry.reding@gmail.com>, <vdumpa@nvidia.com>,
	<jonathanh@nvidia.com>, <rafael@kernel.org>, <lenb@kernel.org>,
	<kevin.tian@intel.com>, <yi.l.liu@intel.com>,
	<baolu.lu@linux.intel.com>,
	<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,
	<linux-kernel@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-tegra@vger.kernel.org>, <linux-acpi@vger.kernel.org>,
	<linux-pci@vger.kernel.org>, <patches@lists.linux.dev>,
	<pjaroszynski@nvidia.com>, <vsethi@nvidia.com>,
	<helgaas@kernel.org>
Subject: Re: [PATCH v3 5/5] pci: Suspend iommu function prior to resetting a device
Date: Thu, 21 Aug 2025 23:14:09 -0700	[thread overview]
Message-ID: <aKgKsXmVWS5NZdUn@Asurada-Nvidia> (raw)
In-Reply-To: <d6b852bc-328a-41af-b125-e250c72c0d22@gmail.com>

On Wed, Aug 20, 2025 at 11:18:52AM +0800, Ethan Zhao wrote:
> On 8/20/2025 5:59 AM, Nicolin Chen wrote:
> >   b) multiple pci_devs; single RID
> > 
> >      In this case, FLR only resets one device, while the IOMMU-
> >      level reset will block the entire RID (i.e. all devices),
> >      since they share the single translation tunnel. This could
> >      break the siblings, if they aren't also being reset along.

> Yup, such alias devices might not have ATS cap. because of they
> are PCI devices or they share the RID(BDF), so checking ATS cap
> condition might be useful here to skip the prepare()/done()

Yea, I agree, yet I think we need it to be "sure" than "might"?

So perhaps we should check alias too. Given that all alias devices
in this case share the same RID and reside in the same iommu_group,
we could iterate the group devices for pci_devs_are_dma_aliases().

> > > 2. Reset PF when its VFs are actvie.
> > 
> >   c) multiple pci_devs with their own RIDs
> > 
> >      In this case, either FLR or IOMMU only resets the PF. That
> >      being said, VFs might be affected since PF is resetting?
> >      If there is an issue, I don't see it coming from the IOMMU-
> >      level reset..

> Each of the PF and its VFs has it owns RID(BDF), but the VFs' life
> depends on the living of PF, resetting PF, means all its VFs are
> lost.
> 
> There is no processing logic about PF and its VFs in FLR() yet.
> my understanding the upper layer callers should consider the
> complexity of such case.
> 
> While we introducing the connection of IOMMU & device in FLR(),
> seems we brought some of the logic from the outside to the inside
> part.
> 
> One method might we don't handle PF either by explicit checking its
> VF configuration existing to skip prepare()/done() ? till we have
> much clearer handling logic about it.

That sounds a good one to start with.

The prepare()/done() functions can internally bypass for devices:

	if (!pci_ats_supported(pci_dev) || pci_sriov_get_totalvfs(pci_dev))
		return 0;
	/* And check alias too */

Thanks
Nicolin

  reply	other threads:[~2025-08-22  6:14 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-11 22:59 [PATCH v3 0/5] Disable ATS via iommu during PCI resets Nicolin Chen
2025-08-11 22:59 ` [PATCH v3 1/5] iommu: Lock group->mutex in iommu_deferred_attach Nicolin Chen
2025-08-15  5:09   ` Baolu Lu
2025-08-15  8:27     ` Tian, Kevin
2025-08-15  8:24   ` Tian, Kevin
2025-08-15 19:26     ` Nicolin Chen
2025-08-18 14:17     ` Jason Gunthorpe
2025-08-18 17:45       ` Nicolin Chen
2025-08-18 18:09         ` Jason Gunthorpe
2025-08-18 18:29           ` Nicolin Chen
2025-08-11 22:59 ` [PATCH v3 2/5] iommu: Pass in gdev to __iommu_device_set_domain Nicolin Chen
2025-08-15  5:18   ` Baolu Lu
2025-08-15  8:29   ` Tian, Kevin
2025-08-11 22:59 ` [PATCH v3 3/5] iommu: Add iommu_get_domain_for_dev_locked() helper Nicolin Chen
2025-08-15  5:28   ` Baolu Lu
2025-08-15 18:48     ` Nicolin Chen
2025-08-18 14:40     ` Jason Gunthorpe
2025-08-19  2:09       ` Baolu Lu
2025-08-15  8:55   ` Tian, Kevin
2025-08-15 18:45     ` Nicolin Chen
2025-08-21  8:07       ` Tian, Kevin
2025-08-21 14:41         ` Nicolin Chen
2025-08-31 23:24           ` Nicolin Chen
2025-08-18 14:39   ` Jason Gunthorpe
2025-08-18 17:22     ` Nicolin Chen
2025-08-18 23:42       ` Jason Gunthorpe
2025-08-19  5:09         ` Nicolin Chen
2025-08-19 12:52           ` Jason Gunthorpe
2025-08-19 17:22             ` Nicolin Chen
2025-08-21 13:13               ` Jason Gunthorpe
2025-08-21 15:22                 ` Nicolin Chen
2025-08-21 18:37                   ` Jason Gunthorpe
2025-08-22  5:11                     ` Nicolin Chen
2025-08-21  8:11       ` Tian, Kevin
2025-08-21 13:14         ` Jason Gunthorpe
2025-08-22  9:45           ` Tian, Kevin
2025-08-22 13:21             ` Jason Gunthorpe
2025-08-11 22:59 ` [PATCH v3 4/5] iommu: Introduce iommu_dev_reset_prepare() and iommu_dev_reset_done() Nicolin Chen
2025-08-15  5:49   ` Baolu Lu
2025-08-15 20:10     ` Nicolin Chen
2025-08-15  9:14   ` Tian, Kevin
2025-08-15 19:45     ` Nicolin Chen
2025-08-11 22:59 ` [PATCH v3 5/5] pci: Suspend iommu function prior to resetting a device Nicolin Chen
2025-08-19 14:12   ` Ethan Zhao
2025-08-19 21:59     ` Nicolin Chen
2025-08-20  3:18       ` Ethan Zhao
2025-08-22  6:14         ` Nicolin Chen [this message]
2025-08-21 13:07       ` Jason Gunthorpe
2025-08-22  6:35         ` Nicolin Chen
2025-08-22 14:08           ` Jason Gunthorpe
2025-08-22 18:50             ` Nicolin Chen
2025-08-28 12:51               ` Jason Gunthorpe
2025-08-28 15:08                 ` Nicolin Chen
2025-08-28 18:46                   ` Jason Gunthorpe
2025-08-28 19:35                     ` Nicolin Chen

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=aKgKsXmVWS5NZdUn@Asurada-Nvidia \
    --to=nicolinc@nvidia.com \
    --cc=angelogioacchino.delregno@collabora.com \
    --cc=baolu.lu@linux.intel.com \
    --cc=bhelgaas@google.com \
    --cc=etzhao1900@gmail.com \
    --cc=helgaas@kernel.org \
    --cc=iommu@lists.linux.dev \
    --cc=jgg@nvidia.com \
    --cc=jonathanh@nvidia.com \
    --cc=joro@8bytes.org \
    --cc=kevin.tian@intel.com \
    --cc=lenb@kernel.org \
    --cc=linux-acpi@vger.kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mediatek@lists.infradead.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=matthias.bgg@gmail.com \
    --cc=patches@lists.linux.dev \
    --cc=pjaroszynski@nvidia.com \
    --cc=rafael@kernel.org \
    --cc=robin.clark@oss.qualcomm.com \
    --cc=robin.murphy@arm.com \
    --cc=thierry.reding@gmail.com \
    --cc=vdumpa@nvidia.com \
    --cc=vsethi@nvidia.com \
    --cc=will@kernel.org \
    --cc=yi.l.liu@intel.com \
    --cc=yong.wu@mediatek.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).